ArtistDesign NoE

ARTIST2 – Execution Platforms Cluster Meeting: Other participants

Luca Benini — 2006-09-01T14:14:20Z

Other Participants

Lothar Thiele ETHZ
Luca Benini UNIBO
Alexandru Andrei LIU
Kai Huang ETHZ
Martino Ruggiero UNIBO
Federico Angiolini UNIBO
Alessio Guerri UNIBO
Simone Medardoni UNIFE
Davide Brunelli UNIBO
Elisabetta Farella UNIBO
Rolf Ernst IDA
Shankar Mahadevan DTU

ARTIST2 – Execution Platforms Cluster Meeting: Presentations and downloads

Luca Benini — 2006-09-01T12:54:36Z

Presentations

Presenter: ESI-Jozef Hooman Title: Performance Research in the Boderc project Abstract: We present an overview of work on performance within the Boderc project. This includes a comparison of performance analysis methods on the radio-navigation system. We also report about industrial performance measurents and modeling. Finally, we mention control strategies, such as event-based control, to improve performance.

Presenter: IDA-Simon Schliecker Title: Analysis of memory and coprocessor accesses on MPSoCs

Presenter: ETHZ-Simon Künzli Title: Hybrid Approach to System-Level Performance Analysis Abstract: In this talk, we will briefly talk about a new, compositional performance evaluation method for embedded systems we developed during the last year. The new method combines existing approaches for system-level performance analysis; a formal method and a simulation-based approach. To enable this combination, we define the interfaces needed between the different performance evaluation methods. As a core of the approach, we propose a method to generate simulation stimuli from analytical models. In addition, we introduce a measure to assess the quality of a generated simulation trace with respect to its analytical description. The combined model was then used for a case study of an application running on a multiprocessor system.

Presenter: DTU- Jan Madsen Title: System Modeling Infrastructure

Presenter: Linköping- Petru Eles Title: ARTIST-Relevant Research from Linköping: latest results Abstract: Recent results which are relevant from the point of view of our work in ARTIST will be presented. We will first present our recent results in the context of communication dominated embedded systems In this context we will mention the timing analysis of the FlexRay Communication Protocol and the timing and buffer analysis for NoCs. Then we will briefly present our results in the context of predictability of multiprocessor applications. Here, we are concentrating on two aspects: (1) execution time estimation for multiprocessor systems with shared memory access and (2) predictability in the presence of transient faults.

Presenter: DEIS - Michela Milano Title: System Design Related Optimization Problems

Presenter: UNIFE- Davide Bertozzi Title: Communication and I/O architecture for highly integrated MPSoC platforms Abstract: As the level of system integration of MPSoC platforms keeps increasing, communication fabrics are evolving to support the communication scalability requirements, while not reverting to revolutionary network-based solutions yet. This results in complex segmented architectures where system performance (and eventually energy) tightly depends on the effectiveness of bus bridges, which are actually becoming true Intellectual Property blocks. At the same time, the I/O architecture is becoming the platform bottleneck, since most of processing data tend to be stored off-chip for storage size and technology reasons. In this presentation, I will illustrate the different performance and architectural requirements posed by the memory controller on the communication infrastructure in order to sustain system performance. Finally, the presentation will highlight the research challenges associated with the optimization of memory controller architecture.

Presenter: UPM- Jose L. Ayala Title: Low-power and Low-temperature Compilation for Embedded Processors Abstract: Advances in process technology allow new embedded devices to run multimedia applications with high computational complexity thanks to Very Large Instruction Word (VLIW) processors and high-performance processors. Also, the continuing advances in semiconductor technology have allowed dramatic performance gains for these archtectures. These improvements are due both to increasing clock rates as well as to advanced support for exploiting instruction-level parallelism and memory locality using the additional transistors available in each process generation. However, as a negative consequence, this causes a significant increase in power dissipation. As technology scales, higher power consumption coupled with smaller< chip area will result in higher power density, which in turn will lead< to higher power temperature on the chip. In fact, extrapolating the changes in microprocessor organization and the device miniaturization, one can project future power density to 200 W/cm2. This requires extensive efforts on cooling techniques which have shown to be complex and highly expensive. In our work, we provide a set of characterization methodologies and compilation-based optimizations which are able to minimize the power consumption and temperature of the device without performance impact. Moreover, traditional source-level transformations have been analyzed and their impact on the thermal behavior of the processor has been evaluated. Finally, this work presents a first attempt to achieve the low-power/low-temperature compilation.

Presenter: UCLM - Francisco Moya Title: An MPSOC Middleware: Network Transparency for on-chip/off-chip Modules

Presenter: ETHZ-Clemens Moser Title: Power management for solar-driven sensor nodes Abstract: Energy harvesting has recently emerged as a viable option to increase the lifetime of sensor nodes. In this field, we have conducted research in order to optimize the energy flow on a sensor node under real-time predictability constraints. The node model we are using consists of three major components: An energy source module, an energy storage module and a processing module. For this scenario, we developed scheduling algorithms which are tailored to the energy-driven nature of this problem. An on-line scheduling algorithm has been constructed (lazy scheduling), which is provably optimal if precise information about the energy resource is available. To this end, both the energy prediction of the energy harvesting module as well as the current energy level of the storage module has to be taken into account. Furthermore, we presented an admittance test that decides for periodic and bursty task sets, whether they can be scheduled without deadline violations. For this purpose, we introduce the concept of energy variability characterization curves (EVCC). Finally, the proposed theory leads to practical techniques for scheduling processes in energy harvesting systems as has been shown in extensive simulation studies.

Presenter: IDA-Arne Hamann Title: Sensitivity analysis & System Robustness Optimization

Presenter: UNIURB: Andrea Acquaviva Title: Energy Awareness in Batteryless Systems Abstract: Environmental energy is becoming a feasible alternative to traditional sources for energy constrained devices such as tiny wireless sensor nodes. To efficiently exploit harvesting energy, innovative management policies must be designed. In this presentation we discuss two examples of energy optimization strategies both in local and network context that show how batteryless devices can profit from environmental energy. First, we present an adaptation strategy based on device reconfiguration that exploits the intrinsic unpredictability of environmental energy to opportunistically trigger task remapping on reconfigurable hardware. Second, we formulate the problem of routing optimization for energy harvesting wireless sensor networks (EHWSNs), where the objective function changes from network lifetime as in battery operated ones, to sustainable workload. We finally present an optimal solution to this problem based on graph algorithms.

43rd Design Automation Conference

Lothar Thiele — 2006-09-01T09:05:54Z

The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event.

DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

44th DAC Special Theme Topic: Automotive Electronics

Including safety critical systems design, bus selection and verification challenges, automotive convenience factors, analog mixed-signal design challenges, automotive as an EDA driver, and issues with FPGA, ASIC and ASSP. Submit your paper beginning Oct. 9, 2006! For more info, see the 44th CFP.

Access it online!

Design Automation and Test in Europe

Jan Madsen, Joseph Sifakis, Lothar Thiele — 2006-09-01T09:00:47Z

The 10th DATE conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. It puts strong emphasis on both ICs/SoCs, reconfigurable hardware and embedded systems, including embedded software.

The five-day event consists of a conference with plenary invited papers, regular papers, panels, hot-topic sessions, tutorials and workshops, two special focus days and a track for executives. The scientific conference is complemented by a commercial exhibition showing the state-of-the-art in design and test tools, methodologies, IP and design services, reconfigurable and other hardware platforms, embedded software, and (industrial) design experiences from different application domains, e.g. automotive, wireless, telecom and multimedia applications. The organisation of user group meetings, fringe meetings, a university booth, a PhD forum, vendor presentations and social events offers a wide variety of extra opportunities to meet and exchange information on relevant issues for the design and test community.

TECHNICAL CONFERENCE

Keynotes, scientific papers, interactive presentations, design records, discussion panels, hot-topics, tutorials and workshops. This year there are two dedicated days of specially focused conference sessions in the following areas of design applications: Ubiquitous Computing and Communications Space and Aeronautics. A full list of topics is available online.

EXHIBITION

April 17-19, 2007 Over 100 companies showing the best in design, verification and test tools and platforms for embedded systems and electronic devices, IP cores and design services.

See it online!

See also the Workshop Organised by Artist!

RTAS

Lothar Thiele — 2006-09-01T08:48:47Z

RTAS 2008 seeks papers describing signicant contributions both to the state of the art and the state of the practice in the broad eld of embedded and open real-time systems and computing. The scope of RTAS 2008 consists of the traditional core area of real-time and embedded systems infrastructure and theory, as well as three additional areas of special emphasis: embedded applications; development, verification, and debug tools for real-time and embedded systems; and embedded systems hardware/software interaction/co-design.

See it online

30. Design Automation for Embedded Systems

Lothar Thiele — 2006-08-29T08:25:55Z

Design Automation for Embedded Systems is a multidisciplinary journal which addresses the systematic design of embedded systems, focusing primarily on tools, methodologies and architectures for embedded systems, including HW/SW co-design, simulation and modeling approaches, synthesis techniques, architectures and design exploration, among others.

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30. Very Large Scale Integration Systems

Lothar Thiele — 2006-08-29T08:19:02Z

Includes all major aspects of the design and implementation of VLSI/ULSI and microelectronic systems. Topics of special interest include: systems specifications, design and partitioning, high performance computing and communication systems, neural networks, wafer-scale integration and multichip module systems and their applications.

See it online!

30. Software Engineering

Lothar Thiele — 2006-08-29T08:15:25Z

The IEEE Transactions on Software Engineering is an archival journal published monthly. We are interested in well-defined theoretical results and empirical studies that have potential impact on the construction, analysis, or management of software.

development and maintenance methods and models, e.g., techniques and principles for the specification, design, and implementation of software systems, including notations and process models
assessment methods, e.g., software tests and validation, reliability models, test and diagnosis procedures, software redundancy and design for error control, and the measurements and evaluation of various aspects of the process and product
software project management, e.g., productivity factors, cost models, schedule and organizational issues, standards
tools and environments, e.g., specific tools, integrated tool environments including the associated architectures, databases, and parallel and distributed processing issues
system issues, e.g., hardware-software trade-off
state-of-the-art surveys that provide a synthesis and comprehensive review of the historical development of one particular area ofinterest.

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30. Computers

Lothar Thiele — 2006-08-29T08:05:34Z

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field. It publishes papers, brief contributions, and comments on research in areas of current interest to the readers.

computer organizations and architectures
operating systems, software systems, and communication protocols
real-time systems and embedded systems
digital devices, computer components, and interconnection networks;
specification, design, prototyping, and testing methods and tools;
performance, fault tolerance, reliability, security, and testability;
case studies and experimental and theoretical evaluations; and
new and important applications and trends.

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30. Computer-Aided Design

Lothar Thiele — 2006-08-29T07:26:16Z

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits areemphasized.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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