Hardware Support for Time Composable CRTE systems
Barcelona Supercomputing Center
The fundamental paradigms for the definition of Critical-Real Time Embedded Systems (CRTES) architectures are changing due to cost pressure, flexibility, extensibility and the demand for increased functional complexity. CRTES have based on the federated architecture paradigm, in which each computer is a fully dedicated unit. Federated Architectures simplify the verification, providing a separation of responsibilities, since every provider can implement the hardware and the software for a particular function, independently from the other suppliers. Moreover as each function is implemented on a different hardware unit, the processors commonly used in the hard real-time domain are simple uniprocessor architectures. However, as the number of functions implemented increase, so the number of units does. Implementing more functions in a system following a Federated Architecture approach implies a high number of hardware units. This makes federated implementations inefficient in terms of size, weight and power consumption.
To cope with such problem, automotive and avionics industries are adopting Integrated Architectures (IA), such as Integrated Modular Avionics (IMA) or Automotive Open System Architecture. One fundamental requirement of IA is to ensure the possibility of incremental qualification, whereby each software partition can be subject to verification and validation – including timing analysis – in isolation, independent of the other partitions, with obvious benefits for cost, time and effort. From the perspective of timing analysis, incremental qualification relies on each hardware and software component that is part of the system, such as the cache at hardware level or the linker at software level, exhibiting the property of time composability. In addition to time composability, CRTES demand for high computation power to support new and more complex functionalities. This required computation power can only be provided by means of more advanced hardware (e.g. cache and multicores).
In this presentation I will talk about hardware support to enable time composability while providing high performance. In particular I will present the MERASA processor architecture: The MERASA architecture is a multicore architecture that can simultaneously run hard and non-hard real-time tasks, providing safe and composable WCET estimations for the HRT tasks and high performance for the NHRT tasks. I will also talk about the feasibility of a probabilistic timing analysis approach, and the hardware to support required to enable it, as a way to provide high performance and time composability.