VINNOVA, Rue du Luxembourg 3, "Sweden House"

Close to metro station Troon, metro line 2

Bus 12 from the airport stops 300m from the location

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Meeting Notes

Participants: Björn, Peter (P), Raimund, Sebastian (from Saarbrücken)

Presentations:

• Peter Puschner: A naive timing-analyzers wish list for time-predictable MPSoC architectures
• Björn Lisper: WCET analysis of code parallelized with the polytope method
• Raimund Kirner: Timing anomalies

Discussions, topics:

1. What to concretely do within the TA activity? Ideas/plans for joint work

Every partner should think seriously about this.

2. Joint position paper on issues in timing analysis for MPSoC/Multicore

It was (again) decided that this is a good idea. We need to decide on the direction and topics. We will have a mail discussion about this, where partners can suggest what to bring up, and then we will distribute the writing work. Björn will coordinate the work. At forthcoming activity meetings we will devote some time to issues regarding the paper.

3. Continuation of WCET Challenge

Reinhard has proposed a new chairman for the steering committee: Reinhard von Hanxleden.

Handling the WCET Challenge is a task for the steering committee. We are however happy to continue the Challenge as an ARTIST event. Last year we were able to get some economical support from ARTIST2 to run the Challenge, maybe we can do the same now?

4. Collect/create benchmark suite for WCET analysis of parallel programs

It was agreed that while it would be very useful to have such a suite, it is also very difficult to agree on one at this point. The problem is that we’re dealing with a much less clean-cut problem now. In the sequential case it is (in principle) quite easy: there, we have a sequential code + processor and then the task is simply to analyze the code for the given hardware. In the parallel case, we are not in that position yet. Rather, we are currently discussing how to make the overall design of the parallel system (both HW and SW) so the system is analyzable at all w.r.t. timing. A common suite of parallel benchmarks can be useful if and when we have better agreement on what the parallel system looks like.

What could be useful already at this stage is to have some cases from different application areas.

5. Common parallel architecture for evaluation (http://www.m5sim.org/ suggested, simulator)

Same answer as for 4.

6. Joint meeting with MPSoC design people at DATE (Nice 20-24 April)

Yes! This meeting is important. Björn will talk with Jan Madsen about it, then we’ll settle for a date during DATE and a preliminary program. Please start to think about what you would like to bring up at this meeting, and perhaps also what you would like the MPSoC design people to tell.

7. Next TA activity meeting(s)

At DATE (with joint MPSoC design meeting)?

In conjunction with ECRTS/WCET workshop June 30?

We made no definite decisions, but the overall feeling was that it will be good with a series of meetings to discuss and synchronize the paper writing.

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