Recent technological trends have led to the introduction of multi-processor
systems on a chip (MPSoCs). It can be expected that the number of processors on such chips will continue to increase. Power efficiency is frequently the driving force having a strong impact on the architectures being used. As a result, heterogeneous architectures incorporating functional units optimized for specific functions are commonly employed.
This technological trend has dramatic consequences on the design technology. Techniques are required, which map sets of applications
onto architectures of MPSoCs. Unfortunately, not much is known about applicable mapping techniques. Mapping could start from task graphs, sequential code or models using other models of computation. Mapping from sequential code requires automatic parallelization techniques.
Parallelization techniques designed for high-performance computing are not always applicable, due to the heterogeneity and since memory access times and communication times are substantially different for MPSoCs.
Aims and scope
The aim of the workshop was to provide a forum for brainstorming and road-mapping the future of mapping applications to MPSoCs. Knowledge about constraints and directions for future MPSoC architectures were collected. Existing mapping techniques were briefly presented and analyzed. Directions for future research were proposed and evaluated.
The scope also included timing analysis for MPSoCs. The workshop resulted in ideas about strategies for research. The goal is to provide in a few years the techniques required for mapping applications efficiently.
The development of new products will be seriously constrained if this goal cannot be reached.