| June 16-17, 2008 Schloss Rheinfels, St. Goar, Germany | organised and funded by Artist |

| 12:00 | Lunch (finger food) |
| 12:45 | Opening (P. Marwedel, TU Dortmund) |
| 13:00 | Future architectures of MPSoC Platforms (John Goodacre, ARM) |
| 14:00 | Mapping techniques (L. Thiele, ETH Zürich) |
| 14:55 | Mapping Flow for Car-Entertainment Applications onto Embedded Multiprocessor Systems (Marco Bekooij, NXP) |
| 15:30 | Break |
| 16:00 | The MAPS project - parallelizing C compiler for MPSoC- (R. Leupers, W. Sheng, RWTH Aachen) |
| 16:35 | Requirements for Application Software and Hardware imposed by Temporal Analysis Techniques (Maarten Wiggers, U. Twente) |
| 17:10 | Brief break |
| 17:15 | Code Synthesis Overview over parallelization techniques I (C. Lengauer, U. Passau) |
| 17:15 | Timing Analysis A Predictable Multiprocessor Design-Flow for Streaming Applications Presentation (Sander Stuijk, TU Eindhoven) |
| 18:00 | Sessions end |
| 18:30 | Departure for social event |
| 19:00 | Social event: wine tasting |
| 9:00 | Future architectures of MPSoC Platforms II (Gerhard Fettweis, TU Dresden) |
| 9:50 | Brief break |
| 09:55 | Code Synthesis Parallelization techniques II (Björn Franke, U. Edinburgh) |
| 09:55 | Timing Analysis Predictable Timing on MPSoC - A Time-Triggered View Presentation (Peter Puschner, TU Wien) |
| 10:30 | Break |
| 11:00 | Code Synthesis From Sequential Application Specification to FPGA-based Heterogeneous MPSoC platform execution (Ed Deprettere, U. Leiden) |
| 11:00 | Timing Analysis Using learning to support the development of embedded systems (Mark Bartlett, U. York) |
| 11:30 | Code Synthesis Mapping to the CELL processor (Martino Ruggiero, U. Bologna) |
| 11:30 | Timing Analysis Discussion on timing analysis issues for MPSoCs |
| 12:00 | Global road mapping discussion |
| 12:30 | Lunch |
| 13:30 | Global road mapping discussion (continued) |
| 14:00 | ArtistDesign internal discussion |
| 15:00 | End of workshop |