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Mapping Applications to MPSoCs 2008
| June 16-17, 2008 Schloss Rheinfels, St. Goar, Germany | organised and funded by ARTIST |
Program & Slides of the 1st Workshop on Mapping of Applications to MPSoCs
Monday, June 16th, 2008
| Opening (P. Marwedel, TU Dortmund) |
| Future architectures of MPSoC Platforms (John Goodacre, ARM) |
| Mapping techniques (L. Thiele, ETH Zürich) |
| Mapping Flow for Car-Entertainment Applications onto Embedded Multiprocessor Systems (Marco Bekooij, NXP) |
| The MAPS project - parallelizing C compiler for MPSoC (R. Leupers, W. Sheng, RWTH Aachen) |
| Requirements for Application Software and Hardware imposed by Temporal Analysis Techniques (Maarten Wiggers, U. Twente) |
| Code Synthesis Overview of parallelization techniques I (C. Lengauer, U. Passau) |
| Timing Analysis A Predictable Multiprocessor Design-Flow for Streaming Applications Presentation (Sander Stuijk, TU Eindhoven) |
Tuesday, June 17th, 2008
| Future architectures of MPSoC Platforms II (Gerhard Fettweis, TU Dresden) |
| Code Synthesis Parallelization techniques II (Björn Franke, U. Edinburgh) |
| Timing Analysis Predictable Timing on MPSoC - A Time-Triggered View Presentation (Peter Puschner, TU Wien) |
| Code Synthesis From Sequential Application Specification to FPGA-based Heterogeneous MPSoC platform execution (Ed Deprettere, U. Leiden) |
| Timing Analysis Using learning to support the development of embedded systems (Mark Bartlett, U. York) |
| Code Synthesis Mapping to the CELL processor (Martino Ruggiero, U. Bologna) |
| Timing Analysis Discussion on timing analysis issues for MPSoCs |
| Global road mapping discussion |
| ArtistDesign internal discussion |
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