Mapping of Applications to MPSoCs

June 16-17, 2008       Schloss Rheinfels, St. Goar, Germany organised and funded by Artist 

Tentative Program of the 1st Workshop on Mapping of Applications to MPSoCs

Note: for all presentation slots, 50% of the time has to be available for discussions!

Monday, June 16th, 2008

12:00 Lunch (finger food)
12:45Opening (P. Marwedel, TU Dortmund)
13:00Future architectures of MPSoC Platforms (John Goodacre, ARM)
14:00Mapping techniques (L. Thiele, ETH Zürich)
14:55Mapping Flow for Car-Entertainment Applications onto Embedded Multiprocessor Systems (Marco Bekooij, NXP)
15:30Break
16:00The MAPS project - parallelizing C compiler for MPSoC- (R. Leupers, W. Sheng, RWTH Aachen)
16:35Requirements for Application Software and Hardware imposed by Temporal Analysis Techniques (Maarten Wiggers, U. Twente)
17:10Brief break
17:15Code Synthesis

Overview over parallelization techniques I (C. Lengauer, U. Passau)
17:15Timing Analysis
A Predictable Multiprocessor Design-Flow for Streaming Applications Presentation (Sander Stuijk, TU Eindhoven)
18:00Sessions end
18:30 Departure for social event
19:00 Social event: wine tasting

Tuesday, June 17th, 2008

9:00Future architectures of MPSoC Platforms II (Gerhard Fettweis, TU Dresden)
9:50Brief break
09:55Code Synthesis
Parallelization techniques II (Björn Franke, U. Edinburgh)
09:55Timing Analysis
Predictable Timing on MPSoC - A Time-Triggered View Presentation (Peter Puschner, TU Wien)
10:30 Break
11:00Code Synthesis
From Sequential Application Specification to FPGA-based Heterogeneous MPSoC platform execution (Ed Deprettere, U. Leiden)
11:00Timing Analysis
Using learning to support the development of embedded systems (Mark Bartlett, U. York)
11:30 Code Synthesis
Mapping to the CELL processor (Martino Ruggiero, U. Bologna)
11:30Timing Analysis
Discussion on timing analysis issues for MPSoCs
12:00Global road mapping discussion
12:30Lunch
13:30 Global road mapping discussion (continued)
14:00ArtistDesign internal discussion
15:00 End of workshop
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