9h00-9h15: Welcome and Introduction


Session 1: AADL based Analysis

9h15-9h40: Eric Senn, Johann Laurent, and Jean-Philippe Diguet. Multi-Level power consumption modelling in the AADL design flow for DSP, GPP, and FPGA

9h40-10h05: Daniel Monteverde, Alfredo Olivero, Sergio Yovine, and Victor Braberman. VTS-based Specification and Verification of Behavioral Properties of AADL Models

10h05-10h30: Mohamed Yassin Chkouri, Anne Robert, Marius Bozga, and Joseph Sifakis. Translating AADL into BIP - Application to the Verification of Real-time Systems


10h30-11h00: Coffee break


Session 2: Transformation and Synthesis

11h00-11h30: Gregor v. Bochmann. Deriving component designs from global requirements

11h30-12h00: Thomas Huining Feng, and Edward A. Lee. Scalable Models Using Model Transformation

12h00-12h30: Nikolay Pakulin, and Vladimir Rubanov. ISE language: the ADL for Efficient Development of Cross Toolkits


12h30-14h00: Lunch break


Session 3: Tools, Applications, Patterns

14h00-14h20: Sabeur Lafi, Roger Champagne, Ammar Kouki, and Jean Belzile. Modeling Radio-Frequency Front-Ends Using SysML: A Case Study of a UMTS Transceiver

14h20-14h40: Matteo Bordin, Marco Panunzio, Carlo Santamaria, and Tullio Vardanega. A Reinterpretation of Patterns to Increase the Expressive Power of Model-Driven Engineering Approaches

14h40-15h00: Marie-Agnes Peraldi-Frati, and Yves Sorel. From high-level modelling of time in MARTE to real-time scheduling analysis

15h00-15h20: Joseph Porter, Gabor Karsai, Peter Volgyesi, Harmon Nine, Peter Humke, Graham Hemingway, Ryan Thibodeaux, and Janos Sztipanovits. Towards Model-Based Integration of Tools and Techniques for Embedded Control System Design, Verification, and Implementation


15h20-15h30: Formation of Break-Out Groups


15h30-16h00: Coffee break


16h00-17h15: Discussion in Break-Out Groups


17h15-17h30: Reports of Break-Out Groups and Conclusions

• From Requirements to Architecture
• Design Languages
• Transformations and PIM/PSM

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