ARTIST Summer School in China 2009

July 19-24, 2009       Tsinghua, China organised and funded by ARTIST 


Professor Luis Almeida

University of Porto, Portugal
Luis Almeida is currently an associate professor at the Electrical and Computer Engineering Department of the University of Porto and a member of the Electronics and Telematics Engineering Institute of Aveiro in which he coordinated the Electronic Systems Lab between 2003 and early 2008. He is also a senior member of the IEEE, Computer Society, member of the Strategic Management Board of the EU/ICT NoE ArtistDesign, leader of the Real-Time Networks activity in that NoE, and a Trustee of the RoboCup Federation.

His current interests are in real-time communication protocols for embedded systems with an emphasis on mechanisms to support predictable operational flexibility as needed for dynamic QoS management, graceful degradation and open distributed real-time systems in general. He is also interested in control architectures for teams of autonomous mobile robots, focusing on distributed architectures to support global coordination and data fusion, and in flexible control approaches, particularly for networked control. He is a co-author of more than 150 refereed publications in international scientific conferences and journals in the areas of interest, and co-author of 3 patents and 6 book chapters, having participated in several EU and national projects and given numerous invited talks and short courses about related topics. He regularly participates in the organization and program committees of scientific events in the Real-Time Systems and Robotics communities, including RTSS, ECRTS, DATE, SIES, WFCS, ETFA and RoboCup.
Real-Time Communication in Embedded Systems:
   Techniques, Technologies and Applications
The proliferation of integrated communication interfaces within embedded computing platforms allowed an unprecedented level of distribution and integration that has been pushing frameworks such as Networked Embedded Systems (NESs), Wireless Sensor Networks (WSNs) and Mobile Ad hoc Networks (MANETs). In many applications, particularly involving transmission of live monitoring data, feedback control data or interactive multimedia data, there are timing constraints that must be respected for the applications to be effective. This requires bounded responses not only from the processors but also from the network. In this course we will analyse the concepts, techniques and technologies used at the network level to provide timely communication. In particular we will start from current trends in embedded systems design and from there we will address the timing issues in the network, the temporal control of communication, the protocol stack and its layers, we will revisit some related protocols covering both wired and wireless technologies, including CAN, FlexRay, Ethernet, WiFi and IEEE 802.15.4, we will analyse the traffic model and scheduling issues, and finally we will discuss some on-going related research projects.

Professor Christoph Kirsch

University of Salzburg, Austria

Christoph Kirsch received the Dr.Ing. degree from Saarland University, Saarbruecken, Germany, in 1999 while at the Max Planck Institute for Computer Science in Saarbruecken. He then worked as Postdoctoral Researcher at the Department of Electrical Engineering and Computer Sciences of the University of California, Berkeley. Since 2004, he is full professor and holds a chair at the Department of Computer Sciences of the University of Salzburg, Austria.

His research interests are in concurrent programming and systems, virtual execution environments, and embedded real-time software. Dr. Kirsch co-invented the Giotto and HTL languages, and leads the JAviator unmanned-aerial-vehicle project for which he received an IBM faculty award in 2007. He co-founded the International Conference on Embedded Software (EMSOFT), has been general co-chair of ESWEEK 2008, and is general chair of LCTES 2009. He has been invited to serve on program committees of CASE, Coordination, DATE, EMSOFT, EUC, EuroSys, LCTES, OOPSLA, RTAS, RTSS, and VEE.
Explicit, Dynamic Memory Management with Temporal and Spatial Guarantees
This course gives an introduction to the problem of explicit, dynamic memory management in systems that require temporal and/or spatial guarantees. Predictable memory management is key to introducing many higher-level programming abstractions to such systems. The course will focus on allocating, deallocating, and accessing contiguous pieces of memory using techniques ranging from basic but unpredictable methods such as Best-fit and First-fit to the latest, fully predictable method called Compact-fit. Students will hear about the fundamental problem of managing contiguous pieces of memory (fragmentation), and learn how to deal with it in general (compaction, coalescing) but also in real time (partial compaction) and in the presence of concurrency (incremental compaction).

Professor Kim Guldstrand Larsen

University of Aalborg, Denmark

Kim Guldstrand Larsen (1957) is Professor in Computer Science at Aalborg University (1993- ), and has been Industrial Professor at Twente University, The Netherlands (2000-2007). He is currently director of CISS, the Centre for Embedded Software Systems, a national centre of excellence within ICT bridging between industry and research (2002- ). He is the leader of the Modeling and Validation Cluster within the ArtistDesign European Network of Excellence, and is director of the DaNES project (Danish Network for Intelligent Embedded Systems).

His research interests include modeling, verification, performance analysis of real-time and embedded systems with application and contributions to concurrency theory and model checking. In particular since 1995 he has been prime investigator of the tool UPPAAL and co-founder of the company UP4ALL International. He has published more than 150 publications in international journals and conferences as well as co-authored 6 software-tools.

He is or has been editorial board member of the journals: Formal Methods in System Design, Theoretical Computer Science and Nordic Journal of Computing. He is a member of the steering committee for the ETAPS conference series, the CONCUR conference series, the TACAS conference series and the FORMATS workshop series. He is member of the Royal Danish Academy of Sciences and Letters, Copenhagen, and is member of the Danish Academy of Technical Sciences.
Validation, Performance Analysis and Synthesis of Embedded Systems
Model-driven development is a key to dealing with the increasing complexity of embedded systems, while reducing the time and cost to market. The use of models should permit early assessment of the functional correctness of a given design as well as requirements for resources (e.g. energy, memory, and bandwidth) and real-time and performance guarantees. Thus, there is a need for quantitative models allowing for timed, stochastic and hybrid phenomena to be modeled and analyzed.
UPPAAL is a tool for modeling, simulating and verifying real-time and hybrid systems, developed collaboratively by BRICS at Aalborg University and Department of Computer Systems at Uppsala University since the beginning of 1995 (see UPPAAL and the branches CORA and TIGA provide an integrated tool environment for modeling, validation, verification and synthesis of real-time systems modeled as networks timed automata, extended with data types and user-defined functions. The lectures will provide details on the expressive power of timed automata in relationship to embedded systems as well as details on the power and working of the UPPAAL verification engine.

During the lectures the demonstration and application of the UPPAAL tool suite will be given on a number of practical and industrial cases. Particular attention will be given to the theory of the underlying formalisms of the UPPAAL tool suite, including: timed automata, priced timed automata, and (priced) timed games addressing a number of associated decision problems related to model-checking and optimal scheduling and strategies. The lectures will highlight the by now classical region-construction underlying the decidability of several of these problems. Also, the frontier of decidability will be drawn including pointing out a number of open problems.

Professor Jan Madsen

Technical University of Denmark

Jan Madsen is Professor in computer-based systems at DTU Informatics at the Technical University of Denmark (2002- ), where he is currently heading the section on Embedded Systems Engineering. He is the leader of the Hardware Platforms and Multiprocessor System-on-Chip Cluster within the EU/IST Network of Excellence ArtistDesign and member of the Strategic Management Board of ArtistDesign. He is member of IEEE and is currently serving as Vice Chair of IEEE Denmark Section.
His research interests are related to design of embedded computer systems. In particular system-level modeling and analysis of multi-core systems realized on a single chip, System-on-Chip, including RTOS modeling and hardware/software codesign, and design methodologies and implementations of embedded systems and wireless sensor networks, including CAD tools. He has published more than 80 publications in international journals and conferences as well as co-authored 8 book chapters and 4 edited books.
Jan Madsen is the lead delegate for Denmark in the Governing Board of the ARTEMIS Joint Undertaking, a new pan-European research initiative for public-private partnership in Embedded Systems. He is on the steering committee of D-ARTEMIS, a national initiative to create awareness of embedded systems and to stimulate participation in ARTEMIS projects. He is site leader in SYSMODEL (funded by ARTEMIS JU) and activity leader of Execution Platforms and Chairman of the Steering Board of DaNES (funded by the Danish Advanced Technology Foundation).
He is serving on the panel of Computer Science in the Swedish National Research Council in 2007 and 2009. He has been Program Chair of DATE’07 and CODES’00, and General Chair of CODES’01. He is member of the steering committee of the CODES-ISSS (ESWEEK). He is or has served on many program committees, including SIES, ARC, NOCS, LCTES, DAC, CODES-ISSS, ISSS, CODES, RTSS, DATE, and PARC.
Mapping Applications onto Multi-Core Platforms
One of the challenges in modern embedded system design is to map the application onto a multi-core platform such that essential requirements are met. In order to do so at an early stage in the design process, where not all parts have been implemented or even designed, a system-level model of the application executing on the multi-core platform is needed. This model should allow for an accurate modeling of the global performance of the system, including the interrelationships among the diverse processors, software processes and physical interfaces and inter-connections. This course gives an introduction to the problem of mapping applications onto multi-core platforms. The process of mapping covers the allocation of tasks to processors of the platform and the definition of their execution order, i.e. the task scheduling. The course will focus on task scheduling for parallel systems. It will cover basic architectures for multi-core platforms (homogeneous and heterogeneous architectures) and how to model these, as well as how to model the application as a parallel program. The course will cover both basic scheduling algorithms (handling static scheduling) and more advanced algorithms, which are able to handle consequences of the, often complex, communication structures of the platform. The course will cover issues of real-time systems, including real-time operating systems (handling dynamic scheduling), as well as other quantitative aspects such as power consumption and memory usage. Finally, the course will give an introduction to how quantitative aspects of such systems may be formally modeled and analyzed.

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