ADSD 2006: Advanced Digital Systems Design

September 25-29, 2006       Lausanne, Switzerland sponsored by Artist 


Introduction to Embedded Systems

Lothar Thiele, ETHZ

The purpose of the module is to provide an overview about embedded systems. Starting from major application areas, we will review several issues that dominate the design of embedded systems. Examples of important considerations are design methodologies, embedded system architectures, design criteria and constraints.

System Design Principles

Lothar Thiele, ETHZ

In this lecture, we will discuss system-level issues related to the overall hardware and software architecture of embedded systems. On the one hand, we will dicuss various principles to design software for embedded systems (time triggered paradigms including cyclic executive scheduling and event triggered paradigms). In addition, we consider the design of embedded systems that are composed of complex blocks like processors, memory, communication units, hardware accelerators and programmable hardware. Based on models to describe the required functionality and the system structure, we will investigate methods to solve the major design problems such as allocation, binding of tasks and interface synthesis. One of the central points will be the exploration of the design space on the system level.

Real-Time Scheduling

Lothar Thiele, ETHZ

It is well acknowledged that the share of software in embedded systems steadily increases. Therefore, the second lecture will be devoted to foundations of real-time operating systems and scheduling. Besides a general introduction into the field, we will focus on hardware/software systems that process streams of data packets which occur in communicating embedded systems. Examples are the transmission and processing of voice and video streams with quality of service constraints that are mixed with other classes of packet oriented data.

VLIW Architectures

Paolo Ienne, EPFL

VLIW ("Very Long Instruction Word") processors achieve high performance by exploiting the finest-grain parallelism of common applications. ILP ("Instruction-Level Parallelism") is available in large amounts in typical multimedia-oriented applications; hence, VLIW processors are not only starting to appear in the general purpose domain (e.g., Intel’s Itanium) but are already somehow established in the Digital Signal Processing and embedded arena (e.g., TI’s 320C6000 platform and STMicroelectronics’ ST200). In contrast to classic processors exploiting ILP (e.g., superscalar processors), VLIW processors do not contain hardware to decide at runtime when and where instructions should be executed; the scheduling task is completely delegated to the compiler. ILP compilers must address a number of challenges to generate an effective static schedule in the absence of key runtime information. ILP extraction techniques are essential for the success of systems based on VLIW processors: the VLIW philosophy is an exemplary case of complexity shift across the hardware/software border. Furthermore, the relative hardware simplicity of VLIW processors makes them good candidates for some emerging embedded-system design methodology, such as extensible and customisable processors.

Embedded Memory Systems

Nigel Topham, Uni Edinburgh

Memory systems are a critical component for embedded processors, often occupying more than half the die area and consuming more than half of the power consumption of a typical embedded processor. It is therefore important for system designers to make appropriate design choices when configuring embedded memory systems. Today most embedded processors have at least a level-1 instruction and data cache, or their equivalent, and possibly also a level-2 cache. Even deeply-embedded systems may require support for virtual memory address translation. This lecture explores the design tradeoffs from the standpoint of performance, die area, and power consumption. The aim is to present methodologies for optimizing each of these three requirements and to describe a number of practical techniques that can be deployed in hardware and software to improve them. Where appropriate, examples of these optimisation techniques in commercial designs will be used to illustrate these concepts.

Memory Architecture Aware Compilation

Peter Marwedel, Uni Dortmund


DSP Architectures for Communications

Heinrich Meyr, RWTH

In order to maximize the bandwidth efficiency in advanced wireless communication systems highly sophisticated algorithms are employed in the receiver. The designer of such a receiver is confronted with the facts that a) the algorithmic complexity grows faster than the processing power of traditional digital signal processors and b) the battery power remains constant. The solution of the task, therefore, requires an entirely new class of signal processing platform, which comprises a large number of different, loosely coupled processing engines, each of which is matched to a particular subtask. In this lecture we discuss the task of the system designer to find the optimum compromise between flexibility (via SW programmability) and computational efficiency measured by the (area x time x energy/task) metrics. We place particular emphasis on the design of ASIP’s, which will become a key element in any heterogeneous signal processing platform. The design of such ASIP’s comprises the joint task of designing the algorithm and the architecture interactively. It has become feasible only recently with the availability of a new generation of system level EDA tools. In the lecture we will discuss a number of practical case studies using the LISATek tool suite of CoWare Inc.

Retargetable Compilers

Rainer Leupers, RWTH

While compiler technology for general-purpose processors is relatively mature in terms of code quality, embedded system design poses new challenges for compiler designers. The high computational efficiency requirements of embedded systems demand for extremely high code quality that comes close to hand-optimized assembly. This is not easily achieved with traditional compiler technology, since embedded processors often show highly dedicated irregular architectures tuned for specific applications. Moreover, compilers for embedded processors must be flexible, or retargetable, so that they can be quickly adapted to varying target processor architectures. This is due to the need for performing architecture exploration for application-specific processors (ASIPs), where the compiler must be included in the exploration loop in order to guarantee an optimal software/hardware match. This lecture gives a brief introduction to compiler technology, architecture exploration methodology, and embedded processor architectures. It describes the new role of compilers as a key technology for the design of ASIPs and focuses on the resulting compiler requirements. In addition, the state-of-the-art in code optimization for domain-specific processors families like Digital Signal Processors and Network Processors will be summarized. The lecture will be concluded with a practical demonstration of the LISATek C Compiler Designer.

Automatic Processor Specialization

Laura Pozzi, Uni Lugano

Customisable embedded processors are quickly becoming available on the market, thus making it possible for designers to speed up execution of applications by \emphshaping the underlying machine to them. In particular, an effective way to customise is that of adding Application-specific Functional Units to a core, implementing \emphInstruction-Set Extensions (ISEs). While ISEs were initially chosen manually by designers, the state of the art on automatic ISE identification is now improving; many algorithms are being proposed for choosing, given the application’s source code, the best ISEs under various constraints. In this course we will see the most successful techniques proposed up to now to automatically customise processors, we will evaluate their effectiveness, analyse compiler techniques exposing high performance ISEs, and finally explore some techniques for effectively implementing automatically chosen ISEs onto hardware.

Power Analysis and Low Power Design / System-Level Power Optimization

Enrico Macii, Politecnico di Torino / Luca Benini, Uni Bologna

This lecture will cover energy optimization techniques from both hardware and software stand-points. It will start with a brief introduction to the energy optimization problem. An overview of the most successful approaches to energy estimation will be provided next, followed by a demonstration of state-of-the-art analysis tools. Energy optimization and management will be addressed in the second part of the lecture. The focus will be on system-level techniques, including software transformations and power management policies.

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