Intercluster activity: Design for Predictability and Performance

Brief State of the Art

The problem of WCET determination has been solved for single tasks and several types of processors and some replacement strategies, including least-recently-used (LRU). Higher degrees of predictability in the cache system can be achieved by taking decisions statically instead of dynamically. Compiler-directed memory management using scratchpad memory, originally developed to decrease energy consumption, also increases time predictability. Reactive processors are also promising because they allow the direct predictable execution of synchronous languages (Esterel), thanks to the direct support of the multi-threading and of the synchronization between threads. Analysis of scheduling policies has been well-researched for single processor systems, but is still not a resolve task for multicore platforms. From the hardware point of view, system interconnects present a significant challenge to predictability, in that they are shared among multiple communication actors (cores, IOs, accelerators, etc.). Time-triggered communication protocols have been proposed, among others, to enhance interconnect robustness and predictability. Techniques for general analysis of timing and researches in predictable, often distributed, embedded systems model messages and communication resources in a similar way as tasks and computation resources. They start from a restricted event model, e.g. periodic, sporadic or periodic with jitter, and have been able to provide analysis results where the interference between event triggered and time triggered computation and/or communication paradigms can be bounded. A unifying approach to performance analysis has beeen proposed based on real-time calculus.

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