Cluster: SW Synthesis, Code Generation and Timing Analysis

This cluster provides software synthesis, code generation and timing analysis tools which are required for modern embedded architectures. A particular focus is on multi-processor systems. The parallelism and communication structures found in such architectures pose a particular challenge.

  • High-Level Objectives 

    here is a continuing demand for higher performance of information processing. This growing demand stimulates using a growing amount of parallelism (including using multiple processors), due to limitations of increasing clock speeds any further. This trend also affects the design of embedded systems. Hardware platforms, containing connected processors, are becoming increasingly parallel. Actually, there are various kinds of connectivity. In multi-processors in a system on a chip (MPSoC), processors are tightly connected and communication is fast. In other cases, networked processors may be less tightly connected and communication may be slower. In this project, we would like to address the issues resulting from the use of multiple processors, in particular in the form of multiple heterogeneous processors on a chip, also containing memory hierarchies and communication interfaces.

  • Brief State of the Art 

    The design of efficient embedded systems is the target of numerous optimization tools. There are clearly too many tools to make any attempt to present a survey in limited space useful. Even within the more restricted area of optimization the memory structure, many approaches have been proposed by computer architects. Due to the increasing speed gap between processors and memories, efforts for improving the performance of systems have been predicted to hit the “memory wall”. Work was done in the context of caches (loop caches, filter caches etc.). However, these approaches have mostly focussed on hardware approaches for reaching the goals. For these approaches, compilers were considered to be black boxes and untouchable.

  • Core participants 

    Core participants in the cluster: "SW Synthesis, Code Generation and Timing Analysis".

  • Affiliated Partners 

    Affiliated partners for the cluster: SW Synthesis, Code Generation and Timing Analysis

  • Main Research Trends  

    Mapping of applications to MPSoCs can be considered as an extension of scheduling. Traditionally, scheduling mostly focused on independent tasks. This assumption is not valid for most applications of embedded systems. Additional research is performed in the multi-core context. Multi-core processors are usually considered to be homogeneous. For embedded systems, this assumption is also not valid. Therefore, new mapping techniques are required. Some papers have been published in this area. It is a trend to combine the mapping problem with non-traditional objectives. For example, minimization of the operating temperatures, maximization of the life-time of processors, and dependability in the presence of failing processors etc are considered. However, these approaches mostly consider tasks as black boxes with little information, for example, on the memory access characteristics. This can lead to sub-optimum mappings. This trend is important in all industrial areas in which high performance embedded computing is required.

  • Industrial Sectors Impacted 

    The work performed in the cluster is relevant for all industrial sectors using embedded software. This includes semiconductor houses, system houses, companies working on audio processing, video processing, data streaming applications in the TV, Set Top boxes, DVD players and recorders, mobile phones, base stations, printers and disk drives. Efficiency of embedded software, in particular the efficiency of memories, is relevant for high-speed embedded systems.

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