COESD 2010

June 15th, 2010      University of Bologna, Italy (within CPAIOR10) organised with Artist partners 

Combinatorial Optimization for Embedded System Design


Iuliana Bacivarov (ETH, Zurich) will give the invited talk at COESD2010; further information is available in the Programme Session.

Brief description of the workshop

in conjunction with CPAIOR2010, 7th International Conference on Integration of Artificial Intelligence (AI) and Operations Research (OR) techniques in Constraint Programming

NOTE: the submission deadline has been postponed to April 7th, 2010

The diffusion of embedded computing systems has grown in the last decade to almost reach ubiquity. From mobile phones and TV to cars and dishwashers, all electrically powered devices we commonly use everyday are digitally controlled by a programmable system. Over 99% of the microprocessors produced today are used in embedded systems, and quite recently the number of embedded systems in use has become larger than the number of humans on the planet. In parallel, a similarly wide technological leap sets new design challenges and new opportunities to exploit advanced combinatorial optimization methods.

Hybrid optimization methods, in particular, are a perfect candidate to deal with the detailed and complex problems involved in the design of moderm systems and applications. This workshop represents an occasion to bring the world of digital system design closer to that of combinatorial optimization; such a meeting presents the chance to tackle new interesting problems, to devise and apply algorithmic methods and to disclose broad economic opportunities.

The highest quality accepted paper will be offered the opportunity to submit an extended version to a special issue of the ACM Transactions on Embedded Computing Systems.

Topics of interest

Algorithmic approaches, benchmark proposals and problem statements are well appreciated. New results may be submitted as well as ongoing works, or summaries of published results. Topics of interest include, but are not limited to:
  • Optimal mapping problems of hardware resources to computer applications
  • Optimal scheduling over multi-resource hardware platforms; this includes:
    • Scheduling problems at the process/task level
    • Instruction scheduling problems
  • Optimal design space exploration problems
    • synthesis of optimal platforms to run specific applications
    • optimal mixed HW/SW implementation of applications
  • FPGA/Coarse grained hardware configuration problems
  • Communication allocation and scheduling for Networks-on-chip
  • Optimal storage allocation and scheduling for complex memory hierarchies
  • Optimal power/thermal-aware resource allocation policies
  • Optimal code parallelization techniques

More in general, works targeting any specific optimization problem arising in the design process of some embedded system are welcome.

Important Dates

- Workshop date: Tuesday 15 June 2010

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