COESD 2010

June 15th, 2010      University of Bologna, Italy (within CPAIOR10) organised with Artist partners 


COESD 2010 - Workshop Programme

All talks last 15’ + 5’ of questions and discussion.

Introductory Session [2:15 PM - 3:00 PM]
  • 2:15 PM: Invited Talk: Iuliana Bacivarov, ETH Zurich
  • 2:55 PM: Q&A + brief discussion

First Session [3:00 PM - 4:00 PM]
  • 3:00 PM: Krzysztof Kuchcinski, "Graph Constraints in Embedded SystemDesign"
  • 3:20 PM: Alessio Bonfietti, "Incremental Throughput Constraint for Synchronous Data-Flow Graphs"
  • 3:40 PM: Giuseppe Tagliavini, "A unified framework for optimal mapping of parallel applications on MPSoC platforms"

Coffee break [4:00 PM - 4:30 PM]

Second Session [4:30 PM - 5:30 PM]
  • 4:30 PM: Enrico Bini, "Optimal Period Selection of a Real-Time Task Set"
  • 4:50 PM: Sergiu Carpov, "Memory bandwidth-constrained parallelism dimensioning for embedded many-core microprocessors"
  • 5:10 PM: Zdravko Karakehayov, "Optimal Clock Rate Control for Energy-Aware Embedded Systems"

About the Invited Talk

Distributed Operation Layer: Efficient Design Space Exploration of Scalable MPSoC

Multi-processor system-on-chip (MPSoC) is one of the most promising and solid paradigm for implementing embedded systems for signal processing in communication, medical, and multi-media applications. MPSoC platforms are heterogeneous by nature as they use multiple computation, communication, memory, and peripheral resources. They allow the parallel execution of (multiple) applications and, at the same time, they offer the flexibility to optimize performance, energy consumption, or cost of the system. Nevertheless, to optimize an MPSoC in the presence of tight time-to-market and budget constraints, a systematic design flow is required.
The distributed operation layer (DOL) is a platform independent MPSoC design flow based on the Kahn Process Network (KPN) model of computation and targeted at real-time multimedia and (array) signal processing applications. The DOL design cycle follows the Y-chart approach, in which the application specification is platform-independent and needs to be related to a concrete architecture by means of an explicit mapping. The optimal mapping solution is searched in the design space by an automated design space exploration loop. In general, the problem of optimally mapping an application to a heterogeneous distributed architecture is known to be NP-complete. In addition, the mapping problem is usually multi-objective such that there is no single optimal solution but a set of Pareto-optimal solutions constituting a so-called Pareto-front. In DOL, the aim of the design space exploration is to compute the set of Pareto-optimal solutions representing different trade-offs in the desig
n space. Based on the (approximated) Pareto-front, the designer chooses the final solution to implement. Design space exploration is built on top of formal performance analysis and automated software synthesis tools. This talk will highlight specific aspects in the DOL design flow, proposing a system-level solution for MPSoC mapping optimization.

Short Biography

Iuliana Bacivarov joined ETH Zürich, Switzerland, as a post-doctoral fellow in the Computer Engineering and Networks Laboratory in 2006. Her research interests include Multi-Processor System-on-Chip (MPSoC) design methods models and tools, in particular system-level models and methods for the performance evaluation and optimization of mapping parallel applications to MPSoCs. Currently, her research is applied to EU-funded large scale research projects related to MPSoC systems: SHAPES, EURETILE, PRO3D, COMBEST, and PREDATOR. She received the MS and PhD degree in Micro and Nano-Electronics from the National Polytechnic Institute of Grenoble, France, in 2003 and 2006, respectively. She received the Electronics Engineer degree from Polytechnic University of Bucharest, Romania in 2002.

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