Research and Integration
- Cluster: Modeling and Validation
- Cluster: SW Synthesis, Code Generation and Timing Analysis
- Cluster: Operating Systems and Networks
- Cluster: Hardware Platforms and MPSoC Design
- Intercluster activity: Design for Adaptivity
- Intercluster activity: Design for Predictability and Performance
Affiliated partners for the cluster: SW Synthesis, Code Generation and Timing Analysis
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Affiliated Industrial+SME Partners
Affiliated industrial and SME partners in the cluster: "SW Synthesis, Code Generation and Timing Analysis".
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Affiliated Academic + International Partners
Affiliated Academic and International Partners in the cluster: "SW Synthesis, Code Generation and Timing Analysis".
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