Affiliated Academic and International Partners in the cluster: "SW Synthesis, Code Generation and Timing Analysis":

Prof. Dr. Sabine Glesner (Technical University of Berlin)

www.pes.cs.tu-berlin.de

• Technical role(s) within ArtistDesign: Activity Leader for Compiler Platform
  Compiler Verification
• Research interests: Compilers, Verification, Embedded Systems and Software, Formal Semantics
• Role in leading conferences/journals/etc in the area
   PC Member of Compiler Construction 2007
   Date’06, Design, Automation and Test in Europe, TPC Member of Topic B9 on Formal Verification
   Workshop Compiler Optimization meets Compiler Verification COCV, ETAPS Conferences, PC Member in 2005 and 2006, Program Co-Chair in 2007
   Workshop Formal Foundations of Embedded Software and Component-Based Software Architectures (FESCA), ETAPS Conferences, PC Member 2005 and 2006
   Editorial Board Member of “Informatik – Forschung und Entwicklung” by Springer, starting with Vol. 21, No. 1
• Notable past projects
   VATES (Verification and Transformation of Embedded Systems), funded by DFG
  Aktionsplan Informatik (Emmy Noether-Program), funded by DFG, support for young researchers to build a research group, with a focus on optimization and verification in the compilation of higher programming languages, from 2004 to 2009
   Correct and Optimizing Compilers for Modern Processor Architectures, funded by a PostDocs excellence program of Baden-Württemberg, Germany, 2003-2005
  Grant in the Wrangell-Habilitation Program of Baden-Württemberg, Germany, 2001-2005
• Awards / Decorations
   Award of the “Forschungszentrum Informatik” for one of the two best PhD theses of the Faculty for Computer Science, University of Karlsruhe, 1998/99
  Member of the “Studienstiftung des deutschen Volkes”, the German national scholarship organization, 1991-1996
   Fulbright grant to study at the University of California, Berkeley, 1993-1994
  Member of the Siemens Internationaler Studenten / Doktorandenkreis, 1993-1999

Dr. Alain Darte

 Scientific leader of Inria Project Compsys (Compilation and Embedded Computing Systems) Laboratoire de l’Informatique du Parallélisme CNRS, Inria, UCBL, ENS-Lyon
http://perso.ens-lyon.fr/alain.darte

• Technical role(s) within ArtistDesign: Activity in automatic parallelization, source to source transformations for high-level synthesis of hardware accelerators, possibly WCET.
• Research interests: Code optimizations for embedded computing systems: back-end code optimizations (SSA form, register allocation, static/JIT compilation), source-to-source code transformations for HLS tools (code rewriting, memory and communication optimizations).
• Role in leading conferences/journals/etc in the area: Editorial board of ACM Transactions on Embedded Computing Systems (ACM TECS). Program committees in 2008-09: SCOPES 2009, PLDI 2008, CC 2008. Before 2008: many DATE, CASES, ASAP, ICS, CGO, etc.
• Notable past projects: Minalogic project SCEPTRE, Collaboration with STMicroelectronics, funded by French Ministry of Research and Région Rhône-Alpes
• Awards / Decorations: Best paper awards: IPDPS 2002, CGO 2007

Professor Ed Deprettere (Leiden Embedded Research Center, Leiden Institute of Advanced Computer Science, Leiden University)

http://www.liacs.nl/ edd/

• Technical roles within ArtistDesign: The group of Ed Deprettere has a strong history of
  working on the Daedalus framework for mapping applications to MPSoCs. Due to
  being an affiliated member of the network, the expertise resulting from the
  design of Daedalus is available in the network. Ed Deprettere and his
  co-worker Todor Stefanov have been actively participating in the Rheinfels
  workshops on mapping of applications to MPSoCs and they have been leading an
  effort on benchmarks for such mappings. They will continue to contribute to
  the key workshop of this activity.
• Research interests: Multiprocessor and multicore execution platforms modeling, programming, and design; parallel programming; models of computation; real-time, high throughput, and predictable processing of multimedia and computer vision applications; pervasive, mobile, and ubiquitous computing.
• Role in leading conferences/journals/etc in the area: program committee CODES; editorial board ’journal of Signal Processing Systems’ (Springer); editorial board ’International Journal of Embedded Systems’ (Inderscience Enterprises Ltd); co-founder and steering committee international symposium on Systems, Architectures, Modeling, and Simulation; program committee IEEE International conference on Application Specific Aystems, Architectures, and
  Processors.
• Notable past projects
  • Ubiquitous Communication (Ubicom): 1996-2000 (Delft Universityi Funding)
  • Artemis and Artemisia: 2000- 2009 (Dutch Progress Funding)
  • Open Source Design Framework ’Daedalus’ (http://daedalus.liacs.nl/
• Awards/decorations
  • Best Paper awards: IEEE Trans on Acoustics, Speech, and Signal Processing 34(5) pp 1054-1063; Best Paper award: IEEE Trans on Signal Processing 39(21) pp 383-394; D.O. Pederson Best Paper Award IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems 27(3) pp 542-555
  • Fellow IEEE, Member ACM

Dr. Björn Franke (Lecturer, University of Edinburgh)

http://homepages.inf.ed.ac.uk/bfranke/Welcome.html

• Technical role(s) within ArtistDesign: Provide a link to work on program analysis and parallelization
• Research interests: Compilers, embedded systems

Prof. Paul Kelly (Imperial College, London)

http://www.doc.ic.ac.uk/ phjk/

• Technical role(s) within ArtistDesign: Provide a link to work on program analysis and parallelization
• Research interests: Software performance optimization

Prof. Abhik Roychoudhury (Associate Professor, National University of Singapore)

http://www.comp.nus.edu.sg/ abhik/

• Technical role(s) within ArtistDesign: Timing Analysis
• Research interests: Software Analysis/Validation, Design Tools for Embedded Systems, Formal Methods in System Design.
• Role in leading conferences/journals/etc in the area: Recent Program Committee work includes:
   Intl. Conf. on Software Engineering (ICSE) 2009 – Tools Track,
   Intl. Symp. on Automated Technology for Verification and Analysis (ATVA) 2009.
• Notable past projects
   “Timing Analysis of Behavioural System Models” (2007 -10) http://www.comp.nus.edu.sg/ abhik/projects/model-timing/
   “EASEL: Engineering Architectures and Software for the Embedded Landscape” (2006-09), Funded by A*STAR Singapore under Embedded and Hybrid Systems Programme.
   “Chronos: Architectural Modelling for Timing Analysis of Embedded Software” (2003 – 07) http://www.comp.nus.edu.sg/ rpembed...
• Awards / Decorations: Tan Kah Kee Young Inventor’s Award 2008.

Professor Soonhoi Ha (Seoul National University)

http://peace.snu.ac.kr/sha

• Technical role(s) within ArtistDesign: The group of Soonhoi Ha has a strong history of working on the HOPES framework for mapping applications to MPSoCs. Due to being an affiliated member of the network, the expertise resulting from the design of HOPES is available in the network. Soonhoi has attended the Rheinfels workshops on mapping of applications to MPSoCs this year. He will be very valuable as an international partner.
• Research interests
   HW/SW codesign methodology based on dataflow model of computation, which includes HW/SW partitioning, design space exploration, HW/SW cosimulation, HW/SW cosynthesis.
   Parallel embedded SW design methodology
   Virtual prototyping systems of parallel embedded systems
• Role in leading conferences/journals/etc in the area: Associated editor of ACM TODAES (ACM transaction on design automation of electronic systems) TPC members of several international conferences: DATE, ASP-DAC, CODES+ISSS, ESTIMedia, ISOCC
   Previous TPC chair: ASP-DAC 2008, CODES+ISSS 2006, ESTIMedia 2005-2006
   Previous general chair: CODES+ISSS 2007
• Notable past projects
   NRL (National Research Lab.) project: “Architecture Optimization and Rapid Prototyping of Embedded Systems based on Hardware-Software Codesign Methodology” – government support during 2001.7 2006.6 Through this project, PeaCE HW/SW codesign environment could be developed successfully.
   “Embedded S/W Design and Verification Techniques for MPSoC” – government support during 2006.3 2007. 2 We established the first version of parallel embedded SW design methodology.
   “New design methodology of next-generation embedded systems with high degree of parallelism” – government support from 2007.3 2010.2. Ongoing project to build the HOPES environment that is a parallel embedded SW design environment.
• Awards/decorations
   National Research Laboratory, Korean Ministry of Science and Technology, 2001-2006.
   Best paper Award, SoC Design Conference, Korea, 2003.
   IEEE CAS Seoul Chapter Best Paper Award, International SoC Design Conference (ISOCC), 2004.
   Excellent Research Achievement 50, Korea Science and Engineering Foundation, 2006
• Further information
   Associated dean for educational affairs, College of Engineering, SNU, Korea (2009.3 2011.2)

Prof. Dr.-Ing. Jürgen Teich

http://www12.informatik.uni-erlangen.de/people/teich/

• Technical role(s) within ArtistDesign: The group of Jürgen Teich has a strong history of
  working on the SystemCoDesigner framework for mapping applications to
  MPSoCs. The group was already present at two ArtistDesign meetings before
  becoming an affiliate. As an affiliated partner, Dr. Teich will continue to
  contribute to solving the very difficult mapping problem.
• Research interests: Hardware/Software Co-Design, ESL synthesis, Design Space Exploration, SystemC-Based Design, Reconfigurable Computing, Organic Computing, Massively parallel MPSoC architectures: Design and Compilation Tools for Parallelization and Synthesis
• Role in leading conferences/journals/etc in the area Program Chair for CODES+ISSS 2007, FPL 2008, ASAP 2010
• Notable past projects Apart from DFG, BMBF, and EU funds, he has successful and continues cooperations with a number of research labs and companies such as IBM, Infineon, Daimler, AUDI, Siemens, Alcatel-Lucent, and Cadence. He is member of two European Networks of Excellence, namely HiPEAC2, the European Network of Excellence on High Performance and Embedded Architecture and Compilation as well as affiliated partner of ARTIST, the European Network of Excellence on Embedded Systems Design. Finally, he was, respectively is member of the following Collaborative Research Centers (SFBs): SFB124, Saarbrücken (Doctorand); SFB 376 Massive Parallelität, Paderborn, subproject coordinator; SFB 614 Selbstoptimierende Systeme des Maschinenbaus, Paderborn, subproject coordinator of two subprojects. Currently: SFB 694 Integration elektronischer Komponenten in mobile Systeme, Erlangen, subproject coordinator.
• Awards/decorations Several best paper awards, e.g., CASES 2001, FPT 2006, HiPEAC Paper Award 2009
   Further information Prof. J. Teich is member of numerous international and national associations such as GI/ITG, Senior Member of the IEEE as well as reviewer for many international scientific journals and conferences such as editor of the Proceedings of DATE (Design, Automation and Test in Europe), program chair of CODES+ISSS 2007, and program chair of FPL 2008. Alone in 2009, he is member of the technical program committees of more than 20 international conferences including ATC, CODES+ISSS, DAC, DATE, FPGA, FCCM, ICFPT, RTAS, ASPDAC, ASAP, EMO, FPL, GECCO, RAW, and VLSI-DAT.
  Since 2003, he coordinates the DFG Priority Program Rekonfigurierbare Rechensysteme. Also in 2003, he has been elected Fachkollegiat for the DFG for the area of Computer Architecture and Embedded Systems, and being re-elected in 2007 for another four year’s period. In Erlangen, he leads a research group on Hardware/Software Co-Design at the Fraunhofer Institut f\"ur Integrierte Schaltungen (IIS). Also in Erlangen, he is currently speaker of the Embedded System Institute (ESI).

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