Mapping of applications to MPSoCs can be considered as an extension of scheduling. Traditionally, scheduling mostly focused on independent tasks. This assumption is not valid for most applications of embedded systems. Additional research is performed in the multi-core context. Multi-core processors are usually considered to be homogeneous. For embedded systems, this assumption is also not valid. Therefore, new mapping techniques are required. Some papers have been published in this area. It is a trend to combine the mapping problem with non-traditional objectives. For example, minimization of the operating temperatures, maximization of the life-time of processors, and dependability in the presence of failing processors etc are considered. However, these approaches mostly consider tasks as black boxes with little information, for example, on the memory access characteristics. This can lead to sub-optimum mappings. This trend is important in all industrial areas in which high performance embedded computing is required.

Taking the well-known (frequently negative) results on automatic parallelization in high-performance computing into account, automatic parallelization is being experimented with in a way which is appropriate for embedded systems. Results obtained (for example at the University of Edinburgh and the University of Passau) indicate that this parallelization is feasible within a restricted scope of applications and architectures. This trend is also important in all industrial areas in which high performance embedded computing is required.

Energy efficiency, initially mostly a topic considered for embedded systems, is now mainstream. Energy availability is continuing to be the most challenging constraint for embedded system design, but performance constraints also exist. Therefore, the design of efficient embedded systems continues being important. Constraints are most dominating for small, mobile products.

The importance of timing is slowly being recognized by larger groups of people. For example, there is increasing interest in the automotive domain. At the same time, researchers are also giving timing issues more attention. In-line with this, the first compiler including a fully integrated WCET estimator was designed recently. This research direction is finding more attention recently.

WCET analysis has so far almost exclusively dealt with sequential code running on uni-processors. The main trend has been towards managing more complex sequential hardware architectures. Increasing the level of automation, e.g., by more advanced analyses constraining the possible program flows, is also a topic of active research. As multi-core and MPSoC architectures arise, the research focus will have to shift towards analysis of parallel systems.

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