There is a continuing demand for higher performance of information processing. This growing demand stimulates using a growing amount of parallelism (including using multiple processors), due to limitations of increasing clock speeds any further. This trend also affects the design of embedded systems. Hardware platforms, containing connected processors, are becoming increasingly parallel. Actually, there are various kinds of connectivity. In multi-processors in a system on a chip (MPSoC), processors are tightly connected and communication is fast. In other cases, networked processors may be less tightly connected and communication may be slower. In this project, we would like to address the issues resulting from the use of multiple processors, in particular in the form of multiple heterogeneous processors on a chip, also containing memory hierarchies and communication interfaces.

These processors can only be exploited if (sets of) applications can be efficiently mapped to heterogeneous processors. Mapping techniques can be either based on task graphs or on sequential applications. The latter require the use of automatic parallelization techniques. In this cluster, we want to provide at least partial solutions to the problem of mapping specifications of embedded systems to networks of embedded processors. These networks will be characterized by different speed parameters reflecting the communication and memory architectures. These parameters will be considered during the mapping. We will focus on mappings from simple sequential code from C or C-like languages. However, we will also look at the generation of code from other specifications, being based, for example, on MATLAB or UML. Such languages could simplify the mapping since such specifications might be inherently parallel (and also more appropriate for embedded systems). In general, mapping techniques will be indispensable for using future architectures.

Timing analysis is also affected by the trend toward the new platforms. Also, timing analysis beyond single processors is required. Timing analysis has to cope with the kind of memory hierarchies found in MPSoCs. Hence, timing analysis will also consider the timing of communication. The overall objective is to provide safe timing guarantees for systems consisting of local memories hierarchies and multiple processors. In addition, overcoming the traditional separation between compilers and timing analysis continues being on the agenda.

The design of efficient embedded systems also requires additional work. In particular, minimizing the energy consumption, addressing the memory wall problem and customizing instruction sets are hot topics, for which integrated approaches from various partners are being extended and exploited.

Partners in this cluster also participate in the activities of the thematic activities of the Transversal Integration work package, where they address adaptivity and predictability of complex systems comprising MPSoCs. Predictability is also to be addressed in the cooperation between partners of the two activities of this cluster.
Partners are also contributing to orthogonal work, such as running workshops on embedded system education, writing text books, and editing a new series of books on embedded systems through Springer (see http://www.springer.com/series/8563).

It is understood that the current project can only help integrating work that provides potential solutions. The actual work on those solutions is mostly paid through other projects

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