Cluster: SW Synthesis, Code Generation and Timing Analysis

Brief State of the Art

Software Synthesis and Code Generation

Mapping applications to MPSoCs is an important topic in various places in the world, due to its extreme relevance for industry. In Europe, Ed Deprettere (U. Leiden) performed significant work, working together with adjacent universities on the DEADALUS tool. Also, the group of Jürgen Teich from the University of Erlangen Nürnberg is proposing the SystemCoDesigner tool. In the automotive context, additional work has been performed at TU Braunschweig. METROPOLIS by Sangiovanni-Vincentelli et al. is a tool working on a global level. CHARMED by Bhattacharyya places emphasis on signal processing applications. Recent tools try to combine task allocation with non-standard cost functions such as energy (e.g. Chang at DAC 2008), temperature (e.g. Ciskun at DATE 2007), lifetime or dependability.

The design of efficient embedded systems is the target of numerous optimization tools. There are clearly too many tools to make any attempt to present a survey in limited space useful. Even within the more restricted area of optimization the memory structure, many approaches have been proposed by computer architects. Due to the increasing speed gap between processors and memories, efforts for improving the performance of systems have been predicted to hit the “memory wall”. Work was done in the context of caches (loop caches, filter caches etc.). However, these approaches have mostly focussed on hardware approaches for reaching the goals. For these approaches, compilers were considered to be black boxes and untouchable. Only few authors (e.g. Barua, Catthoor, Dutt, Kandemir, Egger) have taken a holistic approach, looking at hardware and software issues.

Timing Analysis

Several commercial WCET tools are available. They have experienced positive feedback from extensive industrial use in the automotive and aeronautics industry. The existing tools serve some particular and highly relevant points in this space. AbsInt’s tool for example has been used in the development and the certification of safety-critical systems in the Airbus A380. However, they currently do not serve distributed architectures well.

TU Dortmund demonstrated the integration of compilers and timing analysis and can be considered leading this research area.

(c) Artist Consortium, All Rights Reserved - 2006, 2007, 2008, 2009

Réalisation Axome - Création de sites Internet