Background information
Recent technological trends have led to the introduction of multi-processor systems on a chip (MPSoCs). It can be expected that the number of processors on such chips will continue to increase. Power efficiency is frequently the driving force having a strong impact on the architectures being used. As a result, heterogeneous architectures incorporating functional units optimized for specific functions are commonly employed.
This technological trend has dramatic consequences on the design technology. Techniques are required, which map sets of applications onto architectures of MPSoCs. Unfortunately, not much is known about applicable mapping techniques. Mapping could start from task graphs, sequential code or models using other models of computation. Mapping from sequential code requires automatic parallelization techniques.
Parallelization techniques designed for high-performance computing are not always applicable, due to the heterogeneity and since memory access times and communication times are substantially different for MPSoCs.
Aims and scope
Recent technological trends have led to the introduction of multi-processor systems on a chip (MPSoCs). It can be expected that the number of processors on such chips will continue to increase. Power efficiency is frequently the driving force having a strong impact on the architectures being used. As a result, heterogeneous architectures incorporating functional units optimized for specific functions are commonly employed. This technological trend has dramatic consequences on the design technology. Techniques are required, which map sets of applications onto architectures of MPSoCs. Unfortunately, not much is known about applicable mapping techniques. Mapping could start from task graphs, sequential code or models using other models of computation. Mapping from sequential code requires automatic parallelization techniques. Parallelization techniques designed for high-performance computing are not always applicable, due to the heterogeneity and since memory access times and communication times are substantially different for MPSoCs.
The aim of the workshop is to be a focus point for research on mapping applications to MPSoCs. Directions for future research should be proposed and evaluated. The scope also includes timing analysis for MPSoCs. The goal is to provide - in a few years - the techniques required for mapping applications efficiently. The development of new products will be seriously constrained if this goal
cannot be reached.