The SynDEx tool supports rapid prototyping of reactive application algorithms implemented on distributed heterogeneous hardware architectures [Pernet and Sorel, 2003; Grandpierre et al., 1999; Lavarenne et al., 1991; Forget et al., 2004]. SynDEx, based on the AAA methodology [Sorel 1994], lets the designer specify both the application algorithm and the distributed hardware architecture in a graphical environment, and then automates the mapping and scheduling of functions (called operations) and data-dependences between functions (called data-dependences) on the processors (called operators) and communication media (bus, link, crossbar, etc). During the mapping and scheduling process, which can also be manual, the hardware architecture as well as the application algorithm can be modified to better match the timing and resources constraints. When a sufficiently good solution has been found,SynDEx generates, using executive kernels depending on the processor type, executable codes that can be downloaded and run in real-time onto the distribute target. Algorithms are specified in SynDEx as conditioned data-flow graphs that are indefinitely repeated. The graphs describe directed data-dependences (edges) between operations (vertices), and thus forms a directed acyclic graph. The graphs are conditioned because there may be sub-graphs of operations that are only executed when some value occurs on a specific conditioning input of the sub-graph. This mechanism is equivalent in the data-flow model to the control structure If...Then...Else or Case...Of.... In addition some sub-graphs of operations may be finitely repeated a certain number of times. This mechanism is equivalent in the data-flow model to For i=1 to N Do.... An operation can be hierarchically decomposed into sub-graph of operations. Non decomposable operations are called atomic. The algorithm model has a formal semantics equivalent to synchronous language Signal semantics, and can therefore be verified with tools for this purpose. Two sensors produce constant data for two operations (add and mul) that perform addition and multiply, each of them produces a data for an actuator operation (visuadd and visumul).
Hardware architectures are also specified as graphs but that are not directed. Each architecture graph consists of two types of components interconnected via edges representing bi-directionnal connections. A component may be either an operator (processor, FPGA, ASIC), which sequences operations, or a communication medium, which sequences data-dependences.
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