ArtistDesign Core partners - full consortium
The full consortium of core partners within the ArtistDesign NoE.
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Luis Almeida
Universidade de Aveiro / IEETA
Role within the ArtistDesign European Network of ExcellenceEmail: 
Luis Almeida <lda@det.ua.pt>
Tel: +351 234 370 339
Member of the Strategic Management Board
Participates in
Operating Systems and Networks
Participates in
Intercluster activity: Design for Adaptivity
Leader of the JPRA Activity: “Real-Time Networks”
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Karl-Erik Årzén
LUND University
Email: karlerik@control.lth.se
Tel: +46 46 2228782
Member of the Strategic Management Board
Cluster Leader for
Intercluster activity: Design for Adaptivity
Participates in
Operating Systems and Networks
Leader of the JPRA Transversal Integration Activity: "Design for Adaptivity"
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Luca Benini
University of Bologna
Email: Luca Benini <lbenini@deis.unibo.it>
Tel: (+39) (0) 512093782
Member of the Strategic Management Board
Co-leads
Hardware Platforms and MPSoC Design
Participates in
Intercluster activity: Design for Adaptivity
Participates in
Intercluster activity: Design for Predictability and Performance
Leader of the JPRA Activity: “Platform and MPSoC Design”
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Saddek Bensalem
Verimag Laboratory
Email: Saddek.Bensalem@imag.fr
Tel: +33 456 520 371
Participates in
Modeling and Validation
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Albert Benveniste
INRIA / IRISA
Email: Albert.Benveniste@inria.fr
Tel: +33 299 84 72 35
Cluster Leader for
Modeling and Validation
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Guillem Bernat
University of York, Rapita Systems
Email: Guillem Bernat <bernat@cs.york.ac.uk>
Tel: +44.1904.432772
Participates in
Software Synthesis, Code Generation and Timing Analysis
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Bruno Bouyssounouse
Verimag Laboratory
Email: Bruno.Bouyssounouse@imag.fr
Tel: +33 456 52 03 68
ArtistDesign Technical Coordinator
Member of the Strategic Management Board
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Alan Burns
University of York
Email: Alan Burns <burns@cs.york.ac.uk>
Tel: +44 1904 432779
Member of the Strategic Management Board
Participates in
Operating Systems and Networks
Participates in
Intercluster activity: Design for Adaptivity
Participates in
Intercluster activity: Design for Predictability and Performance
Leader of the JPRA Activity: “Scheduling and Resource Management”
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Giorgio Buttazzo
Scuola Superiore Sant'Anna
Email: Giorgio Buttazzo <giorgio@sssup.it>
Tel: +39 050 882.012
Member of the Strategic Management Board
Cluster Leader for
Operating Systems and Networks
Participates in
Intercluster activity: Design for Adaptivity
Leader of the JPRA Activity: “Resource-Aware Operating Systems”
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Thierry Collette
CEA
Email: Thierry.Collette@cea.fr
Tel: (+33) 16908 6525
Participates in
Hardware Platforms and MPSoC Design
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Petru Eles
Linkoping University
Email: petel@ida.liu.se
Tel: +46 13 281 396
Participates in
Hardware Platforms and MPSoC Design
Participates in
Intercluster activity: Design for Predictability and Performance
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Rolf Ernst
Technische Universität Braunschweig
Email: ernst@ida.ing.tu-bs.de
Tel: (+49) 531 391 3730
Participates in
Hardware Platforms and MPSoC Design
Participates in
Intercluster activity: Design for Predictability and Performance
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Gerhard Fohler
Technische Universität Kaiserslautern - Dept of Real Time and Embedded Systems
Email: Gerhard Fohler <fohler@eit.uni-kl.de>
Tel: +49 631 205 4784
Participates in
Operating Systems and Networks
Participates in
Intercluster activity: Design for Adaptivity
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Sébastien Gérard
CEA / SACLAY
Email: Sebastien.GERARD@cea.fr
Tel: +33 1 69 08 58 24 secr: +33 1 69 08 45 19
Participates in
Modeling and Validation
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Alain Girault
INRIA
Email: Alain.Girault@inria.fr
Tel: +33 476 61 53 51
Participates in
Modeling and Validation
Participates in
Intercluster activity: Design for Predictability and Performance
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Susanne Graf
Verimag Laboratory
Email: Susanne.Graf@imag.fr
Tel: +33 4 56 52 03 52
Cluster Leader for
Modeling and Validation
Participates in
Modeling and Validation
Leader of the JPRA Activity: “Modeling”
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Michael Gonzalez Harbour
Universidad de Cantabria
Email: Michael Gonzalez Harbour <mgh@unican.es>
Tel: +34 942 20 14 83
Participates in
Operating Systems and Networks
Participates in
Intercluster activity: Design for Predictability and Performance
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Boudewijn Haverkort
Participates in
Modeling and Validation
Participates in
Intercluster activity: Integration Driven by Industrial Applications
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Tom A. Henzinger
Ecole Polytechnique Fédérale de Lausanne
Email: Tom Henzinger <tah@eecs.berkeley.edu>
Tel: +41 21 693-5234
Member of the Strategic Management Board
Participates in
Modeling and Validation
Participates in
Intercluster activity: Design for Predictability and Performance
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Axel Jantsch
Royal Institute of Technology
Email: axel@imit.kth.se
Tel: +46 8 790 4124
Participates in
Modeling and Validation
Participates in
Hardware Platforms and MPSoC Design
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Thierry Jéron
INRIA
Email: Thierry.Jeron@irisa.fr
Tel: +33 2 99 84 74 64
Participates in
Modeling and Validation
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Bengt Jonsson
Uppsala University
Email: Bengt.Jonsson@it.uu.se
Tel: +46 18 4713157
Member of the Strategic Management Board
Cluster Leader for
Intercluster activity: Design for Predictability and Performance
Participates in
Modeling and Validation
Leader of the JPRA Transversal Integration Activity: "Design for Predictability and Performance"
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Christoph Kirsch
University of Salzburg
Email: Christoph Kirsch <ck@cs.uni-salzburg.at>
Tel: +43 662 8044 6411
Participates in
Modeling and Validation
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Kim Guldstrad Larsen
Member of the Strategic Management Board
Cluster Leader for
Modeling and Validation
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Christian Lengauer
University of Passau, Germany
Email: Christian.Lengauer@uni-passau.de
Tel: +49 851 509 3070
Participates in
Software Synthesis, Code Generation and Timing Analysis
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Rainer Leupers
RWTH Aachen
Email: Rainer Leupers <leupers@iss.rwth-aachen.de>
Tel: +49 241 80-2830
Participates in
Software Synthesis, Code Generation and Timing Analysis
Participates in
Intercluster activity: Design for Adaptivity
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Björn Lisper
Mälardalen University
Email: Bjorn.Lisper@mdh.se
Tel: +46 21 151709
Participates in
Software Synthesis, Code Generation and Timing Analysis
Participates in
Intercluster activity: Design for Adaptivity
Leader of the JPRA Activity: “Timing Analysis”
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Jan Madsen
Technical University of Denmark
Email: jan@imm.dtu.dk
Tel: +45 4525 3751
Member of the Strategic Management Board
Cluster Leader for
Hardware Platforms and MPSoC Design
Leader of the JPRA Activity: “Platform and MPSoC Analysis”
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Stylianos Mamagkakis
IMEC
Email: Stylianos.Mamagkakis@imec.be
Tel: +32 16 28 89 15
Participates in
Operating Systems and Networks
Participates in
Hardware Platforms and MPSoC Design
Participates in
Intercluster activity: Design for Predictability and Performance
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Peter Marwedel
Technische Universität Dortmund
Email: Peter.Marwedel@udo.edu
Tel: +49 231 755-6111 Secr. +49 231 755-6112
Member of the Strategic Management Board
Cluster Leader for
Software Synthesis, Code Generation and Timing Analysis
Participates in
Intercluster activity: Design for Predictability and Performance
Leader of the JPRA Activity: “Software Synthesis, and Code Generation”
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Peter Puschner
Technische Universität Wien
Email: Peter Pushner <peter@vmars.tuwien.ac.at>
Tel: +431 58801 18227
Participates in
Software Synthesis, Code Generation and Timing Analysis
Participates in
Intercluster activity: Design for Predictability and Performance
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Alberto Sangiovanni-Vincentelli
PARADES
Email: Alberto Sangiovanni-Vincentelli <alberto@parades.rm.cnr.it>
Tel: +39 6 68807923
Member of the Strategic Management Board
Cluster Leader for
Intercluster activity: Integration Driven by Industrial Applications
Participates in
Modeling and Validation
Participates in
Intercluster activity: Design for Predictability and Performance
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Joseph Sifakis
Research Director at Verimag Laboratory
Email: Joseph.Sifakis@imag.fr
Tel: (+33) 4 56 52 03 51
ArtistDesign Scientific Coordinator
Member of the Strategic Management Board
Participates in
Modeling and Validation
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Martin Törngren
KTH - Royal Institute of Technology Stockholm
Email: Martin Törngren <martin@md.kth.se>
Tel: +46 8 790 63 07 +46 70 5136582 (mobile)
Participates in
Modeling and Validation
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Hannu Tenhunen
Royal Institute of Technology
Email: Hannu Tenhuen <hannu@kth.se>
Tel: + 46 8 79 04 119 +358 40 513 6563
Participates in
Hardware Platforms and MPSoC Design
Participates in
Intercluster activity: Design for Adaptivity
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Lothar Thiele
ETH Zurich
Email: Lothar Thiele <thiele@tik.ee.ethz.ch>
Tel: +41 1 6327031
Member of the Strategic Management Board
Participates in
Hardware Platforms and MPSoC Design
Participates in
Intercluster activity: Design for Predictability and Performance
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Eduardo Tovar
Instituto Politécnico do Porto - ISEP-IPP (Portugal)
Email: Eduardo Tovar <emt@dei.isep.ipp.pt>
Tel: +351 22 834 0529
Participates in
Operating Systems and Networks
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Reinhard Wilhelm
Universität des Saarlandes
Email: Reinhard Wilhelm <wilhelm@cs.uni-sb.de>
Tel: +49 681 302 3434
Member of the Strategic Management Board
Participates in
Software Synthesis, Code Generation and Timing Analysis
Participates in
Intercluster activity: Design for Predictability and Performance
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Wang Yi
University of Uppsala
Email: Wang Yi <yi@it.uu.se>
Tel: +46(0)18 4713110 Mobile: +46(0)70 4250293
Participates in
Modeling and Validation
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