Participants
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ArtistDesign Participants
- Strategic Management Board — ArtistDesign NoE
- ArtistDesign Core partners - full consortium
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ArtistDesign Core Partners - by Cluster topics
- Cluster: Modeling and Validation
- Cluster: SW Synthesis, Code Generation and Timing Analysis
- Cluster: Operating Systems and Networks
- Cluster: Hardware Platforms and MPSoC Design
- Intercluster activity: Design for Adaptivity
- Intercluster activity: Design for Predictability and Performance
- Intercluster activity: Integration Driven by Industrial Applications
- ArtistDesign Affiliated Partners - by cluster topics
- Artist2 Participants
Intercluster activity: Design for Predictability and Performance
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Bengt Jonsson
Uppsala University
Role within the ArtistDesign European Network of ExcellenceEmail: 
Bengt.Jonsson@it.uu.se
Tel: +46 18 4713157
Member of the Strategic Management Board
Cluster Leader for
Intercluster activity: Design for Predictability and Performance
Participates in
Modeling and Validation
Leader of the JPRA Transversal Integration Activity: "Design for Predictability and Performance"
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Luca Benini
University of Bologna
Email: Luca Benini <lbenini@deis.unibo.it>
Tel: (+39) (0) 512093782
Member of the Strategic Management Board
Co-leads
Hardware Platforms and MPSoC Design
Participates in
Intercluster activity: Design for Adaptivity
Participates in
Intercluster activity: Design for Predictability and Performance
Leader of the JPRA Activity: “Platform and MPSoC Design”
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Alan Burns
University of York
Email: Alan Burns <burns@cs.york.ac.uk>
Tel: +44 1904 432779
Member of the Strategic Management Board
Participates in
Operating Systems and Networks
Participates in
Intercluster activity: Design for Adaptivity
Participates in
Intercluster activity: Design for Predictability and Performance
Leader of the JPRA Activity: “Scheduling and Resource Management”
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Petru Eles
Linkoping University
Email: petel@ida.liu.se
Tel: +46 13 281 396
Participates in
Hardware Platforms and MPSoC Design
Participates in
Intercluster activity: Design for Predictability and Performance
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Rolf Ernst
Technische Universität Braunschweig
Email: ernst@ida.ing.tu-bs.de
Tel: (+49) 531 391 3730
Participates in
Hardware Platforms and MPSoC Design
Participates in
Intercluster activity: Design for Predictability and Performance
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Alain Girault
INRIA
Email: Alain.Girault@inria.fr
Tel: +33 476 61 53 51
Participates in
Modeling and Validation
Participates in
Intercluster activity: Design for Predictability and Performance
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Michael Gonzalez Harbour
Universidad de Cantabria
Email: Michael Gonzalez Harbour <mgh@unican.es>
Tel: +34 942 20 14 83
Participates in
Operating Systems and Networks
Participates in
Intercluster activity: Design for Predictability and Performance
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Tom A. Henzinger
Ecole Polytechnique Fédérale de Lausanne
Email: Tom Henzinger <tah@eecs.berkeley.edu>
Tel: +41 21 693-5234
Member of the Strategic Management Board
Participates in
Modeling and Validation
Participates in
Intercluster activity: Design for Predictability and Performance
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Stylianos Mamagkakis
IMEC
Email: Stylianos.Mamagkakis@imec.be
Tel: +32 16 28 89 15
Participates in
Operating Systems and Networks
Participates in
Hardware Platforms and MPSoC Design
Participates in
Intercluster activity: Design for Predictability and Performance
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Peter Marwedel
Technische Universität Dortmund
Email: Peter.Marwedel@udo.edu
Tel: +49 231 755-6111 Secr. +49 231 755-6112
Member of the Strategic Management Board
Cluster Leader for
Software Synthesis, Code Generation and Timing Analysis
Participates in
Intercluster activity: Design for Predictability and Performance
Leader of the JPRA Activity: “Software Synthesis, and Code Generation”
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Peter Puschner
Technische Universität Wien
Email: Peter Pushner <peter@vmars.tuwien.ac.at>
Tel: +431 58801 18227
Participates in
Software Synthesis, Code Generation and Timing Analysis
Participates in
Intercluster activity: Design for Predictability and Performance
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Alberto Sangiovanni-Vincentelli
PARADES
Email: Alberto Sangiovanni-Vincentelli <alberto@parades.rm.cnr.it>
Tel: +39 6 68807923
Member of the Strategic Management Board
Cluster Leader for
Intercluster activity: Integration Driven by Industrial Applications
Participates in
Modeling and Validation
Participates in
Intercluster activity: Design for Predictability and Performance
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Lothar Thiele
ETH Zurich
Email: Lothar Thiele <thiele@tik.ee.ethz.ch>
Tel: +41 1 6327031
Member of the Strategic Management Board
Participates in
Hardware Platforms and MPSoC Design
Participates in
Intercluster activity: Design for Predictability and Performance
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Reinhard Wilhelm
Universität des Saarlandes
Email: Reinhard Wilhelm <wilhelm@cs.uni-sb.de>
Tel: +49 681 302 3434
Member of the Strategic Management Board
Participates in
Software Synthesis, Code Generation and Timing Analysis
Participates in
Intercluster activity: Design for Predictability and Performance
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