Luis AlmeidaUniversidade de Aveiro / IEETA
Member of the Strategic Management Board Participates in Operating Systems and Networks Participates in Intercluster activity: Design for Adaptivity Leader of the JPRA Activity: “Real-Time Networks” |
Karl-Erik ÅrzénLUND University
Cluster Leader for Intercluster activity: Design for Adaptivity Participates in Operating Systems and Networks Leader of the JPRA Transversal Integration Activity: "Design for Adaptivity" |
Luca BeniniUniversity of Bologna
Co-leads Hardware Platforms and MPSoC Design Participates in Intercluster activity: Design for Adaptivity Participates in Intercluster activity: Design for Predictability and Performance Leader of the JPRA Activity: “Platform and MPSoC Design” |
Bruno BouyssounouseVerimag Laboratory
Member of the Strategic Management Board |
Alan BurnsUniversity of York
Participates in Operating Systems and Networks Participates in Intercluster activity: Design for Adaptivity Participates in Intercluster activity: Design for Predictability and Performance Leader of the JPRA Activity: “Scheduling and Resource Management” |
Giorgio ButtazzoScuola Superiore Sant'Anna
Cluster Leader for Operating Systems and Networks Participates in Intercluster activity: Design for Adaptivity Leader of the JPRA Activity: “Resource-Aware Operating Systems” |
Tom A. HenzingerEcole Polytechnique Fédérale de Lausanne
Participates in Modeling and Validation Participates in Intercluster activity: Design for Predictability and Performance |
Bengt JonssonUppsala University
Cluster Leader for Intercluster activity: Design for Predictability and Performance Participates in Modeling and Validation Leader of the JPRA Transversal Integration Activity: "Design for Predictability and Performance" |
Kim Guldstrad LarsenMember of the Strategic Management BoardCluster Leader for Modeling and Validation |
Jan MadsenTechnical University of Denmark
Cluster Leader for Hardware Platforms and MPSoC Design Leader of the JPRA Activity: “Platform and MPSoC Analysis” |
Peter MarwedelTechnische Universität Dortmund
Cluster Leader for Software Synthesis, Code Generation and Timing Analysis Participates in Intercluster activity: Design for Predictability and Performance Leader of the JPRA Activity: “Software Synthesis, and Code Generation” |
Alberto Sangiovanni-VincentelliPARADES
Cluster Leader for Intercluster activity: Integration Driven by Industrial Applications Participates in Modeling and Validation Participates in Intercluster activity: Design for Predictability and Performance |
Joseph SifakisResearch Director at Verimag Laboratory
Member of the Strategic Management Board Participates in Modeling and Validation |
Lothar ThieleETH Zurich
Participates in Hardware Platforms and MPSoC Design Participates in Intercluster activity: Design for Predictability and Performance |
Reinhard WilhelmUniversität des Saarlandes
Participates in Software Synthesis, Code Generation and Timing Analysis Participates in Intercluster activity: Design for Predictability and Performance |
(c) Artist Consortium, All Rights Reserved - 2006, 2007, 2008, 2009