Participants
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ArtistDesign Participants
- Strategic Management Board — ArtistDesign NoE
- ArtistDesign Core partners - full consortium
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ArtistDesign Core Partners - by Cluster topics
- Cluster: Modeling and Validation
- Cluster: SW Synthesis, Code Generation and Timing Analysis
- Cluster: Operating Systems and Networks
- Cluster: Hardware Platforms and MPSoC Design
- Intercluster activity: Design for Adaptivity
- Intercluster activity: Design for Predictability and Performance
- Intercluster activity: Integration Driven by Industrial Applications
- ArtistDesign Affiliated Partners - by cluster topics
- Artist2 Participants
Intercluster activity: Design for Adaptivity
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Karl-Erik Årzén
LUND University
Role within the ArtistDesign European Network of ExcellenceEmail: 
karlerik@control.lth.se
Tel: +46 46 2228782
Member of the Strategic Management Board
Cluster Leader for
Intercluster activity: Design for Adaptivity
Participates in
Operating Systems and Networks
Leader of the JPRA Transversal Integration Activity: "Design for Adaptivity"
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Luis Almeida
Universidade de Aveiro / IEETA
Email: Luis Almeida <lda@det.ua.pt>
Tel: +351 234 370 339
Member of the Strategic Management Board
Participates in
Operating Systems and Networks
Participates in
Intercluster activity: Design for Adaptivity
Leader of the JPRA Activity: “Real-Time Networks”
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Luca Benini
University of Bologna
Email: Luca Benini <lbenini@deis.unibo.it>
Tel: (+39) (0) 512093782
Member of the Strategic Management Board
Co-leads
Hardware Platforms and MPSoC Design
Participates in
Intercluster activity: Design for Adaptivity
Participates in
Intercluster activity: Design for Predictability and Performance
Leader of the JPRA Activity: “Platform and MPSoC Design”
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Alan Burns
University of York
Email: Alan Burns <burns@cs.york.ac.uk>
Tel: +44 1904 432779
Member of the Strategic Management Board
Participates in
Operating Systems and Networks
Participates in
Intercluster activity: Design for Adaptivity
Participates in
Intercluster activity: Design for Predictability and Performance
Leader of the JPRA Activity: “Scheduling and Resource Management”
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Giorgio Buttazzo
Scuola Superiore Sant'Anna
Email: Giorgio Buttazzo <giorgio@sssup.it>
Tel: +39 050 882.012
Member of the Strategic Management Board
Cluster Leader for
Operating Systems and Networks
Participates in
Intercluster activity: Design for Adaptivity
Leader of the JPRA Activity: “Resource-Aware Operating Systems”
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Gerhard Fohler
Technische Universität Kaiserslautern - Dept of Real Time and Embedded Systems
Email: Gerhard Fohler <fohler@eit.uni-kl.de>
Tel: +49 631 205 4784
Participates in
Operating Systems and Networks
Participates in
Intercluster activity: Design for Adaptivity
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Rainer Leupers
RWTH Aachen
Email: Rainer Leupers <leupers@iss.rwth-aachen.de>
Tel: +49 241 80-2830
Participates in
Software Synthesis, Code Generation and Timing Analysis
Participates in
Intercluster activity: Design for Adaptivity
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Björn Lisper
Mälardalen University
Email: Bjorn.Lisper@mdh.se
Tel: +46 21 151709
Participates in
Software Synthesis, Code Generation and Timing Analysis
Participates in
Intercluster activity: Design for Adaptivity
Leader of the JPRA Activity: “Timing Analysis”
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Hannu Tenhunen
Royal Institute of Technology
Email: Hannu Tenhuen <hannu@kth.se>
Tel: + 46 8 79 04 119 +358 40 513 6563
Participates in
Hardware Platforms and MPSoC Design
Participates in
Intercluster activity: Design for Adaptivity
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