Affiliated Academic Partners

Prof. David Atienza

Role within the ArtistDesign European Network of Excellence
Participates in Hardware Platforms and MPSoC Design
Collaboration with IMEC vzw.and contribution to the Hardware Platforms and MPSoC cluster and the Software Synthesis, Code Generation and Timing Analysis cluster.

Company or Institution
EPFL, Switzerland, and Complutense University of Madrid, Spain
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Research interests

David Atienza received his MSc and PhD degrees in Computer Science from Complutense University of Madrid (UCM), Spain, and Inter-University Micro-Electronics Center (IMEC), Belgium, in 2001 and 2005, respectively. Currently he is Professor and Director of the Embedded Systems Laboratory (ESL) at Ecole Polytechnique Fédérale de Lausanne, Switzerland, and Adjunct Professor at the Computer Architecture and Automation Department of UCM. His research interests focus on design methodologies for high-performance embedded systems and Systems-on-Chip (SoC), including new thermal management techniques for Multi-Processor SoCs, dynamic memory management and memory hierarchy optimizations for embedded systems, novel architectures for logic and memories in forthcoming nano-scale electronics, Networks-on-Chip interconnection design, and low-power design of embedded systems.
Role in leading conferences/journals/etc in the area In these fields, David Atienza is co-author of more than 90 publications in prestigious journals and international conferences, such as, IEEE TCAD, IEEE Micro, IEEE T-VLSI Systems, ACM TODAES, Elsevier-Integration: The VLSI Journal, DAC, ICCAD, DATE, ASP-DAC, etc. Also, he is part of the Technical Program Committee of the DATE, ICCAD, GLSVLSI, VLSI-SoC, RTAS, SBCCI and PATMOS conferences, and Associate Editor of IEEE Transactions on CAD (in the area of System-Level Design) and Elsevier Integration: The VLSI Journal. He is the general chair of VLSI-SoC 2010 and organizer of several conferences including GLSVLSI ‘09, ISVLSI ‘09 and SBCCI ’09.

Notable past projects

MDDTNSB-B22: “Materials, Devices and Design Technologies for Nanoelectronic Systems Beyond 22 nm CMOS” project
Development of reliability-aware design methodologies for emerging nano-scale electronics.
CMOSAIC project
Design of design 3D stacked processing architectures with interlayer cooling.
TIN2005-ARCHITECT project
HW/SW technologies for the design of high-performance processing systems

Awards / Decorations

David Atienza received the nomination as co-author for the "2004 DAC Best Paper Award" and the "2006 ICCAD Best Paper Award”. In September 2008 he was named IEEE Young Gold Member Coordinator in the area of EDA.

Further Information

Since 2008, he an elected member of the Executive Committee of the IEEE Council of Electronic Design Automation (CEDA).

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