ArtistDesign Final Report and Publishable Summary |
Project Final Report |
Project Publishable Summary |
Y4 Periodic Report |
partner | Deliverable ID | Title |
WP0: Joint Programme of Management Activities (JPMA) | ||
UJF/Verimag | D2-(0.2)-Y4 | Project Management Report (the sum of the 5 chapters below) |
UJF/Verimag | D2-(0.2a)-Y4 | ch. 1 - Executive Summary and Overview |
Aalborg | D2-(0.2b)-Y4 | ch. 2 - Modelling and Validation |
Dortmund | D2-(0.2c)-Y4 | ch. 3 - SW Synthesis, Code Generation and Timing Analysis |
Pisa | D2-(0.2d)-Y4 | ch. 4 - Operating Systems and Networks |
DTU | D2-(0.2e)-Y4 | ch. 5 - Hardware Platforms and MPSoC Design |
Floralis | D1-(0.1)-Y4 | Periodic Report |
WP1: Joint Programme of Integration Activities (JPIA) | ||
UJF/Verimag | D3-(1.0)-Y4 | Integration Activities Report |
WP2: Joint Programme of Activities for Spreading Excellence (JPASE) | ||
UJF/Verimag | D4-(2.0)-Y4 | Spreading Excellence Report |
WP3: Modeling and Validation (JPRA) | ||
UJF/Verimag | D5-(3.1)-Y4 | Modelling |
Aalborg | D6-(3.2)-Y4 | Validation |
WP4: Software Synthesis, Code Generation
| ||
Dortmund | D7-(4.1)-Y4 | Software Synthesis, Code Generation |
Malardalen | D8-(4.2)-Y4 | Timing Analysis |
WP5: Operating Systems and Networks (JPRA) | ||
Pisa | D9-(5.1)-Y4 | Resource-aware Operating Systems |
York | D10-(5.2)-Y4 | Scheduling and Resource Management |
Univ. Porto | D11-(5.3)-Y4 | Real-Time Networks |
WP6: Hardware Platforms and MPSoC (JPRA) | ||
Bologna | D12-(6.1)-Y4 | Platform and MPSoC Design |
DTU | D13-(6.2)-Y4 | Platform and MPSoC Analysis |
WP7: Transversal Integration (JPRA) | ||
Lund | D14-(7.1)-Y4 | Design for Adaptivity |
Uppsala | D15-(7.2)-Y4 | • Design for Predictability • Building Timing Predictable Embedded Systems (unplanned, extra deliverable) |
Trento | D16-(7.3)-Y4 | Integration Driven by Industrial Applications |
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