partner |
Deliverable ID |
Title |
WP0: Joint Programme of Management Activities (JPMA)
|
Floralis |
D1-(0.1)-Y1 |
Periodic Report |
|
|
|
|
D2-(0.2)-Y1 |
Project Activity Report - (the sum of the 5 chapters below) |
UJF/Verimag |
D2-(0.2a)-Y1 |
ch. 1 - Executive Summary and Overview |
Aalborg |
D2-(0.2b)-Y1 |
ch. 2 - Modelling and Validation (updated) |
Dortmund |
D2-(0.2c)-Y1 |
ch. 3 - SW Synthesis, Code Generation and Timing Analysis |
Pisa |
D2-(0.2d)-Y1 |
ch. 4 - Operating Systems and Networks |
DTU |
D2-(0.2e)-Y1 |
ch. 5 - Hardware Platforms and MPSoC Design |
|
|
|
WP1: Joint Programme of Integration Activities (JPIA)
|
UJF/Verimag |
D3-(1.0)-Y1 |
Integration Activities Report |
WP2: Joint Programme of Activities for Spreading Excellence (JPASE)
|
UJF/Verimag |
D4-(2.0)-Y1 |
Spreading Excellence Report |
WP3: Modeling and Validation (JPRA)
|
EPFL |
D5-(3.1)-Y1 |
Modelling |
Aalborg |
D6-(3.2)-Y1 |
Validation |
|
|
|
WP4: Software Synthesis, Code Generation
and Timing Analysis (JPRA)
|
Dortmund |
D7-(4.1)-Y1 |
Software Synthesis, Code Generation |
Saarland |
D8-(4.2)-Y1 |
Timing Analysis |
|
|
|
WP5: Operating Systems and Networks (JPRA)
|
Pisa |
D9-(5.1)-Y1 |
Resource-aware Operating Systems |
York |
D10-(5.2)-Y1 |
Scheduling and Resource Management |
Aveiro |
D11-(5.3)-Y1 |
Embedded Real-Time Networking |
WP6: Hardware Platforms and MPSoC (JPRA)
|
Bologna |
D12-(6.1)-Y1 |
Platform and MPSoC Design |
DTU |
D13-(6.2)-Y1 |
Platform and MPSoC Analysis |
|
|
|
WP7: Transversal Integration (JPRA)
|
Lund |
D14-(7.1)-Y1 |
Design for Adaptivity |
Uppsala |
D15-(7.2)-Y1 |
Design for Predictability |
PARADES |
D16-(7.3)-Y1 |
Integration Driven by Industrial Applications |