Mapping Applications to MPSoCs 2009

June 29-30, 2009       Schloss Rheinfels, St. Goar, Germany organised and funded by ARTIST 

Final Program

Monday, June 29th, 2009

11:45 Lunch (finger food)
12:20 Peter Marwedel Opening
12:30 Soonhoi Ha (Seoul National U., KR) Programming-platform based Design of MPSoCs: The HOPES Approach
13:15 Jürgen Teich (U. Erlangen, D) SystemCoDesigner - Automatic Design Space Exploration and Prototyping from Behavioral Models
14:00 Qiang Xu (Chinese University, Hong Kong, CN) Minimizing Energy Consumption of MPSoCs under Lifetime Reliability Constraints
14:45 Tajana Simunic (UCSD, US) Energy and thermal management in MPSOCs
15:30 Break
16:00 E. Deprettere (U Leiden, NL) with contributions by Todor Stefanov (U. Leiden, NL), Iuliana Bacivarov (ETHZ, CH) and Bastian Ristau (TU Dresden, D) Benchmarking; contribution by I. Bacivarov
16:55 Björn Franke (U. Edinburgh, UK) Towards a Holistic Approach to Auto-Parallelization: Integrating Profile-Driven Parallelism Detection and Machine-Learning Based Mapping
17:20 Marco Bekooij (NXP, NL) Automatic parallelization for embedded multiprocessor systems with non-uniform memory access latencies
17:45 Fabrizio Ferrandi (Polytechnico di Milano) Mapping and Scheduling of Parallel C Applications with Ant Colony Optimization onto
Heterogeneous Reconfigurable MPSoCs
18:10 Session ends
18:30 Departure for social event
19:00 Social event: cruise on the Rhine river (passing the Loreley rock)

Tuesday, June 30th, 2008

9:00 Per Larsen (TU Lyngby, DK) Data-dependencies and Thread Interaction in Parallel Loops
9:25 Michael Claßen (U. Passau, D) Introducing the GCC to the Polyhedron Model
09:50 Gerard Smit (TU Twente, NL) Run-time Spatial Mapping on MPSoCs
10:15 Break
10:45 Iuliana Bacivarov (ETHZ, CH) An Integrated Software Design Flow for Mapping Stream-Oriented Applications to Tile-Based MPSoCs
11:10 Anastasia Stulova (RWTH Aachen, D) MAPS and a high-level virtual platform (MVP)
11:35 Alessio Bonfietti (U. Bologna, I) Throughput constraint for Synchronous Data Flow Graphs
12:00 Lunch
13:15 Henrik Theiling (AbsInt, D) How Unthoughtful Resource Sharing Counteracts WCETAnalysis
13:40 Mircean Negrean (TU Braunschweig, D) Timing Analysis on Complex Real-Time Automotive Multicore Architectures
14:05 Discussion
14:45 Tea break/end of workshop
15:15 Mnemee demo
Open to everyone, not part of ArtistDesign workshop.

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